Acer Aspire One 722_Compal_LA-7071P_P1VE6_Rev1.0.pdf

(842 KB) Pobierz
A
B
C
D
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PCB DAZ0I200101
ZZZ0
ZZZ0
ZZZ1
ZZZ1
ZZZ2
ZZZ2
ZZZ3
ZZZ3
ZZZ4
ZZZ4
ZZZ5
ZZZ5
MB DA60000KP10
USB IO/B DA60000KQ10
HDD/B DA400011R10
LED/B DA400011T10
TP/B DA400013910
PCB
M/B
DAZ@
PCB
M/B
DAZ@
LA-7071P
M/B
DA@
LA-7071P
M/B
DA@
LS-7071P
USB IO/B
DA@
LS-7071P
USB IO/B
DA@
LS-7074P
HDD/B
DA@
LS-7074P
HDD/B
DA@
LS-7075P
LED/B
DA@
LS-7075P
LED/B
DA@
LA-7076P
TP/B
DA@
LA-7076P
TP/B
DA@
1
1
Compal Confidential
P1VE6 LA7071P Schematics Document
2
2
AMD Ontario Processor with DDRIII + Hudson M1
11.6" M/B
2011-03-17
3
3
Rev : 1.0
4
4
Compal Electronics, Inc.
Compal Electronics, Inc.
Compal Electronics, Inc.
Security Classification
Security Classification
Security Classification
Compal Secret Data
Compal Secret Data
Compal Secret Data
2010/11/09
2010/11/09
2010/11/09
2012/11/09
2012/11/09
2012/11/09
Title
Title
Title
Issued Date
Issued Date
Issued Date
Deciphered Date
Deciphered Date
Deciphered Date
Cover Page
Cover Page
Cover Page
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Size
Size
Size
Document Number
Document Number
Document Number
Rev
Rev
Rev
P1VE6 Schematics
P1VE6 Schematics
P1VE6 Schematics
Custom
Custom
Custom
1.0
1.0
1.0
Date:
Date:
Date:
Thursday, March 17, 2011
Thursday, March 17, 2011
Thursday, March 17, 2011
Sheet
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1464419894.765.png 1464419894.876.png 1464419894.987.png 1464419894.1097.png 1464419894.001.png 1464419894.112.png 1464419894.223.png 1464419894.251.png 1464419894.262.png 1464419894.273.png 1464419894.284.png 1464419894.294.png 1464419894.305.png 1464419894.316.png 1464419894.327.png 1464419894.338.png 1464419894.349.png 1464419894.360.png 1464419894.371.png 1464419894.382.png 1464419894.393.png 1464419894.404.png 1464419894.415.png 1464419894.426.png 1464419894.437.png 1464419894.448.png 1464419894.458.png 1464419894.469.png 1464419894.480.png 1464419894.491.png 1464419894.502.png 1464419894.513.png 1464419894.524.png 1464419894.535.png 1464419894.546.png 1464419894.557.png 1464419894.568.png 1464419894.579.png 1464419894.590.png 1464419894.601.png 1464419894.612.png 1464419894.623.png 1464419894.634.png 1464419894.645.png 1464419894.656.png 1464419894.667.png 1464419894.678.png 1464419894.689.png 1464419894.700.png 1464419894.711.png 1464419894.722.png 1464419894.733.png 1464419894.744.png
 
A
B
C
D
E
Compal Confidential
Model Name : P1VE6
Brazos Platform
File Name : LA-7071P
HDMI
AMD
Ontario FT1
APU
BGA 413-Ball
Memory Bus (DDRIII)
Dual Channel
1
RGB
1
204 Pin DDRIII SO-DIMM x2
BANK 0, 1, 2, 3
LVDS
1.5V DDRIII 800/1066
6.4G/8.5G
100M/133M
Page 7 , 8
19mm X 19mm
Page 4,5,6
HDMI Conn.
Page 10
D-Sub Conn.
Page 11
LVDS Conn.
Page 9
UMI x4
Gen.1
USB Conn.x2
(Left Side)
Port 0 , 1
USB Conn.x1
(Right Side)
Port 2
Camera
Bluetooth
Port 7
Card Reader
RTS 5138
2.5GT/s
Port 5
per Lane
Port 6
IO/B
Page 25
Page 9
Page 20
Page 19
Fan Circuit
2
2
PWM
USB
Page 27
AMD
3.3V 48MHz
PCI-Express X3
Hudson M1
HD Audio
3.3V 24MHz
100MHz
PCIE Gen1 2.5GT/S
FCH
SATA Gen1 1.5GT/S ,Gen2 3GT/S
3G Card
100MHz
BGA 605-Ball
Port 1
Port 3
Port 2
Port 3, 9
23mm X 23mm
WWAN
WLAN
LAN(10/100)
Page 20
Page 12 ~ 16
JMINI1
JMINI2
AR8158
SIM Card
Port 4
Page 20
Media processor
Wireless Card
HDD
Port 1
Port 3
Port 2
(2.5")
Page 20
Page 21
Page 18
LPC
33MHz
Port 0
Page 22
3
3
RJ-45
WLAN
Port 8
Page 21
Page 18
ENE KB930
Small Board
Page 26
IO/B
LS-7071P
HDD/B
LS-7074P
HDA Codec+AMP
CX20584
Page 17
RTC Ckt.
LED/B
LS-7072P
TP BTN/B
Page 12
LS-7073P
BIOS ROM
2MB
HP Jack x1
MIC Jack x1
IO/B
4
4
Power Button
Page 27
Page 23
Compal Electronics, Inc.
Compal Electronics, Inc.
Compal Electronics, Inc.
Security Classification
Security Classification
Security Classification
Compal Secret Data
Compal Secret Data
Compal Secret Data
DC/DC Interface Ckt.
2010/11/09
2010/11/09
2010/11/09
2012/11/09
2012/11/09
2012/11/09
Title
Title
Title
Issued Date
Issued Date
Issued Date
Deciphered Date
Deciphered Date
Deciphered Date
Block Diagrams
Block Diagrams
Block Diagrams
Page 28
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Size
Size
Size
Document Number
Document Number
Document Number
Rev
Rev
Rev
P1VE6 Schematics
P1VE6 Schematics
P1VE6 Schematics
B
B
B
1.0
1.0
1.0
Date:
Date:
Date:
Thursday, March 17, 2011
Thursday, March 17, 2011
Thursday, March 17, 2011
Sheet
Sheet
Sheet
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1464419894.766.png 1464419894.777.png 1464419894.788.png 1464419894.799.png 1464419894.810.png 1464419894.821.png 1464419894.832.png 1464419894.843.png 1464419894.854.png 1464419894.865.png 1464419894.877.png 1464419894.888.png 1464419894.899.png 1464419894.910.png 1464419894.921.png 1464419894.932.png 1464419894.943.png 1464419894.954.png 1464419894.965.png 1464419894.976.png 1464419894.988.png 1464419894.999.png 1464419894.1010.png 1464419894.1021.png 1464419894.1032.png 1464419894.1043.png 1464419894.1053.png 1464419894.1064.png 1464419894.1075.png 1464419894.1086.png 1464419894.1098.png 1464419894.1109.png 1464419894.1120.png 1464419894.1131.png 1464419894.1142.png 1464419894.1153.png 1464419894.1164.png 1464419894.1175.png 1464419894.1186.png 1464419894.1197.png 1464419894.002.png 1464419894.013.png 1464419894.024.png 1464419894.035.png 1464419894.046.png 1464419894.057.png 1464419894.068.png 1464419894.079.png 1464419894.090.png 1464419894.101.png 1464419894.113.png 1464419894.124.png 1464419894.135.png 1464419894.146.png 1464419894.157.png 1464419894.168.png 1464419894.179.png 1464419894.190.png 1464419894.201.png 1464419894.212.png 1464419894.224.png 1464419894.235.png 1464419894.243.png 1464419894.244.png 1464419894.245.png 1464419894.246.png 1464419894.247.png 1464419894.248.png 1464419894.249.png 1464419894.250.png 1464419894.252.png 1464419894.253.png 1464419894.254.png 1464419894.255.png 1464419894.256.png 1464419894.257.png 1464419894.258.png 1464419894.259.png 1464419894.260.png 1464419894.261.png 1464419894.263.png 1464419894.264.png 1464419894.265.png 1464419894.266.png 1464419894.267.png 1464419894.268.png 1464419894.269.png 1464419894.270.png 1464419894.271.png 1464419894.272.png 1464419894.274.png 1464419894.275.png 1464419894.276.png 1464419894.277.png 1464419894.278.png 1464419894.279.png 1464419894.280.png 1464419894.281.png 1464419894.282.png 1464419894.283.png 1464419894.285.png 1464419894.286.png 1464419894.287.png
 
A
B
C
D
E
Voltage Rails
Brazos
PCIE Port List
FCH Hudson-M1
USB Port List
USB1.1
FCH Hudson-M1
SATA Port List
SATA0
SATA1
SATA2
SATA3
SATA4
SATA5
Power Plane
Description
S1
S3
S5
VIN
B+
Adapter power supply (19V)
AC or battery power rail for power circuit.
Core voltage for CPU (0.7-1.2V)
N/A
N/A
N/A
N/A
PCIE0
PCIE1
PCIE2
PCIE3
HDD
N/A
N/A
Port0
Port1
NC
NC
NC
+APU_CORE
ON
OFF
OFF
NC
+APU_CORE_NB
1.0V switched power rail
ON
OFF
OFF
NC
1
+1.5V
1.5V power rail for CPU VDDIO and DDRIII
ON
ON
OFF
1
USB2.0
NC
NC
NC
+0.75VS
0.75VS switched power rail for DDR terminator
ON
OFF
OFF
+1.05VS
1.05V switched power rail for NB VDDC & VGA
ON
OFF
OFF
Port0
Port1
Port2
Port3
Port4
Port5
Port6
Port7
Port8
Port9
Port10
Port11
Port12
Port13
Left conn
PCIE0
PCIE1
PCIE2
PCIE3
NC
+1.1VS
1.1VS switched power rail
ON
OFF
OFF
Left conn
WWAN
+1.8VS
1.8V switched power rail
ON
OFF
OFF
+3VALW
3.3V always on power rail
ON
ON
ON*
Right conn
LAN
+1.1VALW
1.1V always on power rail
ON
ON
ON*
WWAN
SIM
WLAN
+3VS
3.3V switched power rail
ON
OFF
OFF
+1.5VS
1.5VS switched power rail
ON
OFF
OFF
+5VALW
5V always on power rail
ON
ON
ON*
USB Camera
CardReader
BT
WiMax
WWAN
+5VS
5V switched power rail
ON
OFF
OFF
+VSB
VSB always on power rail
ON
ON
ON
ON*
ON
+RTCBATT
RTC power
ON
Note : ON* means that this power plane is ON only with AC power available, otherwise it is OFF.
2
2
EC SM Bus1 address
Device
EC SM Bus2 address
NC
NC
NC
NC
Address
HEX
Device
Address
HEX
16H
98H
Smart Battery
0001-011xb
SB-TSI
1001-100xb
SM Bus Controller 0
Board ID / SKU ID Table for AD channel
(FCH_SMB1 ~ FCH_SMB4, SMB_ALERT#)
Vcc
+3VALW
100K +/- 5%
Device
Address
HEX
Ra
Board ID
APU SIC/SID (FCH_SMB3)
Rb
V
min
V
typ
V AD_BID max
PCB Revision
AD_BID
AD_BID
H_THERMTRIP# (FCH_ALERT#)
*
0
1
2
3
0
8.2K +/- 5%
0 V
0.216 V
0 V
0 V
0.1
0.250 V
0.289 V
0.2
18K +/- 5%
33K +/- 5%
56K +/- 5%
100K +/- 5%
200K +/- 5%
0.436 V
0.712 V
0.503 V
0.819 V
0.538 V
0.875 V
SM Bus Controller 1
3
(FCH_SMB0)
4
5
6
7
1.036 V
1.453 V
1.185 V
1.264 V
3
1.650 V
1.759 V
Device
Address
HEX
1.935 V
2.500 V
2.200 V
3.300 V
2.341 V
NC
3.300 V
DDR DIMM1 (FCH_SMB0)
1001-000xb
90
SMBUS Control Table
BOM Structure
Source
BATT
DIMM
MINI Card
LCD DDC ROM
HDMI DDC ROM
APU
EC_SMB_CK1
EC_SMB_DA1
EC_SMB_CK2
EC_SMB_DA2
KB930
V
HDMI@ : HDMI function
BT@ : BT function
CONN@ : Connetors
45@ : 45 Level
KB930
V
HDMI_DATA
HDMI_CLK
APU FT1
V
3G@ : 3G function
EDID_DATA
EDID_CLK
FCH_SMDAT0
FCH_SMCLK0
APU FT1
V
N3G@ : None 3G function
4
4
CMBS@ : Combo Jack POPO noise Solution
NCMBS@: None Combo Jack POPO noise Solution
FCH M1
V
V
Compal Electronics, Inc.
Compal Electronics, Inc.
Compal Electronics, Inc.
Security Classification
Security Classification
Security Classification
Compal Secret Data
Compal Secret Data
Compal Secret Data
2010/11/09
2010/11/09
2010/11/09
2012/11/09
2012/11/09
2012/11/09
Title
Title
Title
Issued Date
Issued Date
Issued Date
Deciphered Date
Deciphered Date
Deciphered Date
Notes List
Notes List
Notes List
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Size
Size
Size
Document Number
Document Number
Document Number
Rev
Rev
Rev
P1VE6 Schematics
P1VE6 Schematics
P1VE6 Schematics
B
B
B
1.0
1.0
1.0
Date:
Date:
Date:
Thursday, March 17, 2011
Thursday, March 17, 2011
Thursday, March 17, 2011
Sheet
Sheet
Sheet
3
3
3
of
of
of
37
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A
B
C
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E
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5
4
3
2
1
Display
APU C50 P/N change to SA00004KD50
Tock 2010/12/30
R9
R352
@
LVDS
eDP
mount
@
*
SA00004KD50
U1B
U1B
mount
APU_SVD
+1.8VS
HDMI_TX2P_C
DP_ZVSS
C1
C1
1
2
.1U_0402_16V7K
.1U_0402_16V7K
A8
H3
R1
R1
1
2
150_0402_1%
150_0402_1%
<10>
HDMI_TX2P
TDP1_TXP0
DP_ZVSS
@
@
C6
C6
.1U_0402_16V7K
.1U_0402_16V7K
HDMI_TX2N_C
1
1
2
B8
<10>
HDMI_TX2N
TDP1_TXN0
G2
DP_BLON
APU_ENBKL <26>
APU_ENVDD <9>
APU_BLPWM <9>
C433
100P_0402_50V8J
C433
100P_0402_50V8J
C2
C2
.1U_0402_16V7K
.1U_0402_16V7K
HDMI_TX1P_C
1
2
B9
H2
<10>
HDMI_TX1P
TDP1_TXP1
DP_DIGON
HDMI_TX1N_C
C3
C3
1
2
.1U_0402_16V7K
.1U_0402_16V7K
A9
H1
<10>
HDMI_TX1N
TDP1_TXN1
DP_VARY_BL
2
D
R3
R3
1K_0402_5%
1K_0402_5%
APU_SVC
D
1
2
APU_SVD
HDMI_TX0P_C
R4
R4
1
2
1K_0402_5%
1K_0402_5%
C7
C7
1
2
.1U_0402_16V7K
.1U_0402_16V7K
D10
<10>
HDMI_TX0P
TDP1_TXP2
C8
C8
.1U_0402_16V7K
.1U_0402_16V7K
HDMI_TX0N_C
HDMI_CLK
1
2
C10
B2
<10>
HDMI_TX0N
TDP1_TXN2
TDP1_AUXP
HDMI_CLK
<10>
C2
HDMI_DATA
HDMI_DATA
<10>
TDP1_AUXN
R8
R8
510_0402_1%
510_0402_1%
TEST_25_L
APU_SVC
C4
C4
.1U_0402_16V7K
.1U_0402_16V7K
HDMI_CLKP_C
8/25 Pull-up 100k(@ R352) to +3VS
on LTDP0_HPD for eDP
1
2
1
2
A10
<10>
HDMI_CLKP
TDP1_TXP3
R6
R6
1K_0402_5%
1K_0402_5%
TEST36
C5
C5
.1U_0402_16V7K
.1U_0402_16V7K
HDMI_CLKN_C
1
2
1
2
B10
C1
<10>
HDMI_CLKN
HDMI_DET
<10>
TDP1_TXN3
TDP1_HPD
@
@
1
+3VS
EDID_CLK
EDID_DATA
B5
A3
EDID_CLK
<9>
<9>
LVDS_A2
LTDP0_TXP0
LTDP0_AUXP
C432
100P_0402_50V8J
C432
100P_0402_50V8J
R352
R352
@
@
100K_0402_5%
100K_0402_5%
A5
B3
1
2
EDID_DATA
<9>
+3VS
<9>
LVDS_A2#
LTDP0_TXN0
LTDP0_AUXN
R10
R10
10K_0402_5%
10K_0402_5%
HDMI_DATA
HDMI_CLK
1
2
2
LTDP0_HPD
R11
R11
1
2
10K_0402_5%
10K_0402_5%
D6
D3
R9
R9
1
2
100K_0402_5%
100K_0402_5%
<9>
LVDS_A1
LTDP0_TXP1
LTDP0_HPD
Reserve C432, C433, C434, C435
Michael 2010/11/18
C6
<9>
LVDS_A1#
LTDP0_TXN1
C12
eDP@
eDP@
DAC_RED
DAC_RED
<11>
R13
R13
1K_0402_5%
1K_0402_5%
APU_PROCHOT#
R12
R12
150_0402_1%
150_0402_1%
R389
R389
0_0402_5%
0_0402_5%
DMIC_CLK
1
2
A6
D13
1
2
1
2
<9>
LVDS_A0
DMIC_CLK
<9,17>
LTDP0_TXP2
DAC_REDB
APU_ALERT#_R
APU_SIC
APU_SID
APU_SID
R14
R14
1
2
1K_0402_5%
1K_0402_5%
B6
A12
<9>
LVDS_A0#
LTDP0_TXN2
DAC_GREEN
DAC_GRN
<11>
R16
R16
1K_0402_5%
1K_0402_5%
R15
R15
150_0402_1%
150_0402_1%
1
2
B12
1
2
DAC_GREENB
Reserve R389 for eDP function
Tock 2010/12/30
R17
R17
1
2
1K_0402_5%
1K_0402_5%
@
@
D8
A13
1
<9>
LVDS_ACLK
LTDP0_TXP3
DAC_BLUE
DAC_BLU
<11>
R18
R18
150_0402_1%
150_0402_1%
C8
B13
1
2
<9>
LVDS_ACLK#
LTDP0_TXN3
DAC_BLUEB
C435
100P_0402_50V8J
C435
100P_0402_50V8J
Change R10, R11 to RP1
Michael 2010/12/23
V2
E1
<12>
APU_CLK
CLKIN_H
DAC_HSYNC
CRT_HSYNC <11>
CRT_VSYNC <11>
CRT_DDC_CLK
2
V1
E2
<12>
APU_CLK#
CLKIN_L
DAC_VSYNC
D2
F2
<12>
DISP_CLK
<11>
DISP_CLKIN_H
DAC_SCL
D1
D4
<12>
DISP_CLK#
DISP_CLKIN_L
DAC_SDA
CRT_DDC_DATA
<11>
LDT_RST#
DAC_ZVSS
C405
C405
1
2
100P_0402_50V8J
100P_0402_50V8J
J1
D12
R19
R19
1
2
499_0402_1%
499_0402_1%
<36>
APU_SVC
SVC
DAC_ZVSS
Power Circuit
J2
<36>
APU_SVD
SVD
10/05 Add 100p(C405) on LDT_RST#
R1
TEST4
APU_SIC
APU_SID
10/01 Remove T1,T3~T7,T11,T12,T31,T32
P3
R2
SIC
TEST5
9/9 Change R24 from @ to mount R26 from mount to @
P4
R6
SID
TEST6
APU_SIC
T5
TEST14
9/15 Change R24 from mount to @
T3
E4
TEST15
R20
R20
1
2
1K_0402_5%
1K_0402_5%
<12>
LDT_RST#
RESET_L
TEST15
C
@
@
C
T4
K4
1
<12>
APU_PWRGD
PWROK
TEST16
L1
TEST17
C434
100P_0402_50V8J
C434
100P_0402_50V8J
APU_PROCHOT#
APU_THERMTRIP#
TEST18
R21
R21
1K_0402_5%
1K_0402_5%
U1
L2
1
2
PROCHOT_L
TEST18
APU_PROCHOT#
TEST19
R22
R22
1K_0402_5%
1K_0402_5%
U2
M2
1
2
2
THERMTRIP_L
TEST19
APU_ALERT#_R
TEST25_H
TEST_25_L
@
@
R24
R24
1
@
@
2
0_0402_5%
0_0402_5%
T2
K1
R25
R25
1
2
510_0402_1%
510_0402_1%
1
<14>
APU_ALERT#_FCH
ALERT_L
TEST25_H
R26
R26
@
@
0_0402_5%
0_0402_5%
1
2
K2
<26>
APU_ALERT#_EC
TEST25_L
APU_TDI
APU_TDO
APU_TCK
APU_TMS
APU_TRST#
APU_DBRDY
APU_DBREQ#
C429
100P_0402_50V8J
C429
100P_0402_50V8J
N2
L5
TDI
TEST28_H
Connection to EC, FCH input need to pull-down
N1
M5
2
TDO
TEST28_L
TEST31
P1
M21
T8
PAD T8
PAD
TCK
TEST31
Add C429 for APU_PROCHOT#
Michael 2010/11/18
TEST33_H
TEST33_L
C9
C9
0.1U_0402_16V4Z
0.1U_0402_16V4Z
R28
R28
51_0402_1%
51_0402_1%
P2
J18
1
2
1
2
TMS
TEST33_H
M4
J19
C10
C10
1
2
0.1U_0402_16V4Z
0.1U_0402_16V4Z
R29
R29
1
2
51_0402_1%
51_0402_1%
TRST_L
TEST33_L
M3
U15
DBRDY
TEST34_H
Close to APU
M1
T15
DBREQ_L
TEST34_L
TEST35
R30
R30
@
@
1K_0402_5%
1K_0402_5%
H4
1
2
TEST35
R23
R23
1
@
@
2
0_0402_5%
0_0402_5%
APU_PROCHOT#
F4
N5
TEST36
TEST37
<36>
APU_VDDNB_RUN_FB_H
VDDCR_NB_SENSE
TEST36
<12>
FCH_PROCHOT#
Power Circuit
R386
R386
1K_0402_5%
1K_0402_5%
G1
R5
T13
PAD T13
PAD
1
2
+1.8VS
<36>
APU_VDD0_RUN_FB_H
VDDCR_CPU_SENSE
TEST37
R27
R27
0_0402_5%
0_0402_5%
1
2
F3
T14PAD
T14PAD
<26>
EC_PROCHOT#
VDDIO_MEM_S_SENSE
9/9 Add R386 (1k@) to +1.8VS on TEST35
9/13 Change R30 from mount to @, R386 from @ to mount (AMD Recommend)
R379
R379
0_0402_5%
0_0402_5%
1
2
F1
<36>
APU_VDD0_RUN_FB_L
VSS_SENSE
Power Circuit
K3
TEST38
R380
R380
0_0402_5%
0_0402_5%
1
2
B4
T1
<36>
APU_VDDNB_RUN_FB_L
ALLOW_STOP# <12>
RSVD_1
DMAACTIVE_L
+3VS
W11
RSVD_2
R31
R31
1K_0402_5%
1K_0402_5%
V5
1
2
+1.8VS
RSVD_3
S IC ONTARIO CMC50AFPB22GT 1G BGA ABO!
S IC ONTARIO CMC50AFPB22GT 1G BGA ABO!
ALLOW_STOP#
9/6 Add R379, R380 for APU_VDDNB_RUN_FB_L
@
@
1
R32
10K_0402_5%
<BOM Structure>
8/31 Change U1 P/N to SA00004DF00 S IC ONTARIO ZM121034B1238 1.2G BGA 413P
C438
100P_0402_50V8J
C438
100P_0402_50V8J
2
R33
1K_0402_5%
Reserve C438 for ALLOW_STOP#
Michael 2010/11/18
B
B
Q1
Q1
APU_THERMTRIP#
3
1
H_THERMTRIP#
<13>
MMBT3904_NL_SOT23-3
MMBT3904_NL_SOT23-3
+1.8VS
1
2
R34
R34
@
@
0_0402_5%
0_0402_5%
9/17 Remove JHDT1 R40, R44, R45, R46 , Add T26~T32
If FCH internal pull-up disabled, level-shifter could be deleted.
Need BIOS to disable internal pull-up!!
9/20 Delete R41~R43
AMD Debug
APU_TRST#
R37
R37
2
1
1K_0402_5%
1K_0402_5%
APU_TDI
R38
R38
2
1
1K_0402_5%
1K_0402_5%
+3VS
2N7002DW-T/R7
APU_TMS
R36
R36
1K_0402_5%
1K_0402_5%
2
1
APU_TCK
R35
R35
1K_0402_5%
1K_0402_5%
2
1
Vgs(th): min 1.0V
Typ 1.6V
Max 2.0V
R39
10K_0402_5%
@
APU_PWRGD
1
C421
100P_0402_50V8J
@
APU_TDO
APU_PWRGD
LDT_RST#
T29 PAD
T29 PAD
If Q8 or R429, R432 implemented,
EC side pull-up need to be mounted
2
R5
R5
300_0402_5%
300_0402_5%
2
1
R7
R7
300_0402_5%
300_0402_5%
2
1
DMN66D0LDW-7_SOT363-6
DMN66D0LDW-7_SOT363-6
APU_DBRDY
T30 PAD
T30 PAD
APU_SID
EC_SMB_DA
@
@
FCH_SID
T0 FCH
Reserve C421 for APU_PWRGD
Michael 2010/11/18
1
6
1
2
FCH_SID <13>
EC_SMB_DA2 <26>
APU_DBREQ#
R47
R47
0_0402_5%
0_0402_5%
R2
R2
2
1
300_0402_5%
300_0402_5%
EC_SMB_DA2
TO EC
1
2
A
A
@
@
R48
R48
0_0402_5%
0_0402_5%
Q2A
Q2A
1
2
R49
R49
0_0402_5%
0_0402_5%
8/19 Change Q2A Q2B SB00000DH00 (S TR DMN66D0LDW-7 2N SOT363-6)
DMN66D0LDW-7_SOT363-6
DMN66D0LDW-7_SOT363-6
Compal Electronics, Inc.
Compal Electronics, Inc.
Compal Electronics, Inc.
Security Classification
Security Classification
Security Classification
Compal Secret Data
Compal Secret Data
Compal Secret Data
APU_SIC
EC_SMB_CK
@
@
FCH_SIC
T0 FCH
4
3
1
2
FCH_SIC <13>
EC_SMB_CK2 <26>
R50
R50
0_0402_5%
0_0402_5%
2010/11/09
2010/11/09
2010/11/09
2012/11/09
2012/11/09
2012/11/09
Title
Title
Title
Issued Date
Issued Date
Issued Date
Deciphered Date
Deciphered Date
Deciphered Date
EC_SMB_CK2
TO EC
FT1 CTRL/DP/CRT
FT1 CTRL/DP/CRT
FT1 CTRL/DP/CRT
1
2
@
@
R51
R51
0_0402_5%
0_0402_5%
Q2B
Q2B
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Size
Size
Size
Document Number
Document Number
Document Number
Rev
Rev
Rev
1
2
R52
R52
0_0402_5%
0_0402_5%
Custom
Custom
Custom
P1VE6 Schematics
P1VE6 Schematics
P1VE6 Schematics
1.0
1.0
1.0
Date:
Date:
Date:
Thursday, March 17, 2011
Thursday, March 17, 2011
Thursday, March 17, 2011
Sheet
Sheet
Sheet
4
4
4
of
of
of
37
37
37
5
4
3
2
1
1464419894.454.png 1464419894.455.png 1464419894.456.png 1464419894.457.png 1464419894.459.png 1464419894.460.png 1464419894.461.png 1464419894.462.png 1464419894.463.png 1464419894.464.png 1464419894.465.png 1464419894.466.png 1464419894.467.png 1464419894.468.png 1464419894.470.png 1464419894.471.png 1464419894.472.png 1464419894.473.png 1464419894.474.png 1464419894.475.png 1464419894.476.png 1464419894.477.png 1464419894.478.png 1464419894.479.png 1464419894.481.png 1464419894.482.png 1464419894.483.png 1464419894.484.png 1464419894.485.png 1464419894.486.png 1464419894.487.png 1464419894.488.png 1464419894.489.png 1464419894.490.png 1464419894.492.png 1464419894.493.png 1464419894.494.png 1464419894.495.png 1464419894.496.png 1464419894.497.png 1464419894.498.png 1464419894.499.png 1464419894.500.png 1464419894.501.png 1464419894.503.png 1464419894.504.png 1464419894.505.png 1464419894.506.png 1464419894.507.png 1464419894.508.png 1464419894.509.png 1464419894.510.png 1464419894.511.png 1464419894.512.png 1464419894.514.png 1464419894.515.png 1464419894.516.png 1464419894.517.png 1464419894.518.png 1464419894.519.png 1464419894.520.png 1464419894.521.png 1464419894.522.png 1464419894.523.png 1464419894.525.png 1464419894.526.png 1464419894.527.png 1464419894.528.png 1464419894.529.png 1464419894.530.png 1464419894.531.png 1464419894.532.png 1464419894.533.png 1464419894.534.png 1464419894.536.png 1464419894.537.png 1464419894.538.png 1464419894.539.png 1464419894.540.png 1464419894.541.png 1464419894.542.png 1464419894.543.png 1464419894.544.png 1464419894.545.png 1464419894.547.png 1464419894.548.png 1464419894.549.png 1464419894.550.png 1464419894.551.png 1464419894.552.png 1464419894.553.png 1464419894.554.png 1464419894.555.png 1464419894.556.png 1464419894.558.png 1464419894.559.png 1464419894.560.png 1464419894.561.png 1464419894.562.png 1464419894.563.png 1464419894.564.png 1464419894.565.png 1464419894.566.png 1464419894.567.png 1464419894.569.png 1464419894.570.png 1464419894.571.png 1464419894.572.png 1464419894.573.png 1464419894.574.png 1464419894.575.png 1464419894.576.png 1464419894.577.png 1464419894.578.png 1464419894.580.png 1464419894.581.png 1464419894.582.png 1464419894.583.png 1464419894.584.png 1464419894.585.png 1464419894.586.png 1464419894.587.png 1464419894.588.png 1464419894.589.png 1464419894.591.png 1464419894.592.png 1464419894.593.png 1464419894.594.png 1464419894.595.png 1464419894.596.png 1464419894.597.png 1464419894.598.png 1464419894.599.png 1464419894.600.png 1464419894.602.png 1464419894.603.png 1464419894.604.png 1464419894.605.png 1464419894.606.png 1464419894.607.png 1464419894.608.png 1464419894.609.png 1464419894.610.png 1464419894.611.png 1464419894.613.png 1464419894.614.png 1464419894.615.png 1464419894.616.png 1464419894.617.png 1464419894.618.png 1464419894.619.png 1464419894.620.png 1464419894.621.png 1464419894.622.png 1464419894.624.png 1464419894.625.png 1464419894.626.png 1464419894.627.png 1464419894.628.png 1464419894.629.png 1464419894.630.png 1464419894.631.png 1464419894.632.png 1464419894.633.png 1464419894.635.png 1464419894.636.png 1464419894.637.png 1464419894.638.png 1464419894.639.png 1464419894.640.png 1464419894.641.png 1464419894.642.png 1464419894.643.png 1464419894.644.png 1464419894.646.png 1464419894.647.png 1464419894.648.png 1464419894.649.png 1464419894.650.png 1464419894.651.png 1464419894.652.png 1464419894.653.png 1464419894.654.png 1464419894.655.png 1464419894.657.png 1464419894.658.png 1464419894.659.png 1464419894.660.png 1464419894.661.png 1464419894.662.png 1464419894.663.png 1464419894.664.png 1464419894.665.png 1464419894.666.png 1464419894.668.png 1464419894.669.png 1464419894.670.png 1464419894.671.png 1464419894.672.png 1464419894.673.png 1464419894.674.png 1464419894.675.png 1464419894.676.png 1464419894.677.png 1464419894.679.png 1464419894.680.png 1464419894.681.png 1464419894.682.png 1464419894.683.png 1464419894.684.png 1464419894.685.png 1464419894.686.png 1464419894.687.png 1464419894.688.png 1464419894.690.png 1464419894.691.png 1464419894.692.png 1464419894.693.png 1464419894.694.png 1464419894.695.png 1464419894.696.png 1464419894.697.png 1464419894.698.png 1464419894.699.png 1464419894.701.png 1464419894.702.png 1464419894.703.png 1464419894.704.png 1464419894.705.png 1464419894.706.png 1464419894.707.png 1464419894.708.png 1464419894.709.png 1464419894.710.png 1464419894.712.png 1464419894.713.png 1464419894.714.png 1464419894.715.png 1464419894.716.png 1464419894.717.png 1464419894.718.png 1464419894.719.png 1464419894.720.png 1464419894.721.png 1464419894.723.png 1464419894.724.png 1464419894.725.png 1464419894.726.png 1464419894.727.png 1464419894.728.png 1464419894.729.png 1464419894.730.png 1464419894.731.png 1464419894.732.png 1464419894.734.png 1464419894.735.png 1464419894.736.png 1464419894.737.png 1464419894.738.png 1464419894.739.png 1464419894.740.png 1464419894.741.png 1464419894.742.png 1464419894.743.png 1464419894.745.png 1464419894.746.png 1464419894.747.png 1464419894.748.png 1464419894.749.png 1464419894.750.png 1464419894.751.png 1464419894.752.png 1464419894.753.png 1464419894.754.png 1464419894.755.png 1464419894.756.png 1464419894.757.png 1464419894.758.png 1464419894.759.png 1464419894.760.png 1464419894.761.png 1464419894.762.png 1464419894.763.png 1464419894.764.png 1464419894.767.png 1464419894.768.png 1464419894.769.png 1464419894.770.png 1464419894.771.png 1464419894.772.png 1464419894.773.png 1464419894.774.png 1464419894.775.png 1464419894.776.png 1464419894.778.png 1464419894.779.png 1464419894.780.png 1464419894.781.png 1464419894.782.png 1464419894.783.png 1464419894.784.png 1464419894.785.png 1464419894.786.png 1464419894.787.png 1464419894.789.png 1464419894.790.png 1464419894.791.png 1464419894.792.png 1464419894.793.png 1464419894.794.png 1464419894.795.png 1464419894.796.png 1464419894.797.png 1464419894.798.png 1464419894.800.png 1464419894.801.png 1464419894.802.png 1464419894.803.png 1464419894.804.png 1464419894.805.png 1464419894.806.png 1464419894.807.png 1464419894.808.png 1464419894.809.png 1464419894.811.png 1464419894.812.png 1464419894.813.png 1464419894.814.png 1464419894.815.png 1464419894.816.png 1464419894.817.png 1464419894.818.png 1464419894.819.png 1464419894.820.png 1464419894.822.png 1464419894.823.png 1464419894.824.png 1464419894.825.png 1464419894.826.png 1464419894.827.png 1464419894.828.png 1464419894.829.png 1464419894.830.png 1464419894.831.png 1464419894.833.png 1464419894.834.png 1464419894.835.png 1464419894.836.png 1464419894.837.png 1464419894.838.png 1464419894.839.png 1464419894.840.png 1464419894.841.png 1464419894.842.png 1464419894.844.png 1464419894.845.png 1464419894.846.png 1464419894.847.png 1464419894.848.png 1464419894.849.png 1464419894.850.png 1464419894.851.png 1464419894.852.png 1464419894.853.png 1464419894.855.png 1464419894.856.png 1464419894.857.png 1464419894.858.png 1464419894.859.png 1464419894.860.png 1464419894.861.png 1464419894.862.png 1464419894.863.png 1464419894.864.png 1464419894.866.png 1464419894.867.png 1464419894.868.png 1464419894.869.png 1464419894.870.png 1464419894.871.png 1464419894.872.png 1464419894.873.png 1464419894.874.png 1464419894.875.png 1464419894.878.png 1464419894.879.png 1464419894.880.png 1464419894.881.png 1464419894.882.png 1464419894.883.png 1464419894.884.png 1464419894.885.png 1464419894.886.png 1464419894.887.png 1464419894.889.png 1464419894.890.png 1464419894.891.png 1464419894.892.png 1464419894.893.png 1464419894.894.png 1464419894.895.png 1464419894.896.png 1464419894.897.png 1464419894.898.png 1464419894.900.png 1464419894.901.png 1464419894.902.png 1464419894.903.png 1464419894.904.png 1464419894.905.png 1464419894.906.png 1464419894.907.png 1464419894.908.png 1464419894.909.png 1464419894.911.png 1464419894.912.png 1464419894.913.png 1464419894.914.png 1464419894.915.png 1464419894.916.png 1464419894.917.png 1464419894.918.png 1464419894.919.png 1464419894.920.png 1464419894.922.png 1464419894.923.png 1464419894.924.png 1464419894.925.png 1464419894.926.png 1464419894.927.png 1464419894.928.png 1464419894.929.png 1464419894.930.png 1464419894.931.png 1464419894.933.png 1464419894.934.png 1464419894.935.png 1464419894.936.png 1464419894.937.png 1464419894.938.png 1464419894.939.png 1464419894.940.png 1464419894.941.png 1464419894.942.png 1464419894.944.png 1464419894.945.png 1464419894.946.png 1464419894.947.png 1464419894.948.png 1464419894.949.png 1464419894.950.png 1464419894.951.png 1464419894.952.png 1464419894.953.png 1464419894.955.png 1464419894.956.png 1464419894.957.png 1464419894.958.png 1464419894.959.png 1464419894.960.png 1464419894.961.png 1464419894.962.png 1464419894.963.png 1464419894.964.png 1464419894.966.png 1464419894.967.png 1464419894.968.png 1464419894.969.png 1464419894.970.png 1464419894.971.png 1464419894.972.png 1464419894.973.png 1464419894.974.png 1464419894.975.png 1464419894.977.png 1464419894.978.png 1464419894.979.png 1464419894.980.png 1464419894.981.png 1464419894.982.png 1464419894.983.png 1464419894.984.png 1464419894.985.png 1464419894.986.png 1464419894.989.png 1464419894.990.png 1464419894.991.png 1464419894.992.png 1464419894.993.png 1464419894.994.png 1464419894.995.png 1464419894.996.png 1464419894.997.png 1464419894.998.png 1464419894.1000.png 1464419894.1001.png 1464419894.1002.png 1464419894.1003.png 1464419894.1004.png 1464419894.1005.png 1464419894.1006.png 1464419894.1007.png 1464419894.1008.png 1464419894.1009.png 1464419894.1011.png 1464419894.1012.png 1464419894.1013.png 1464419894.1014.png 1464419894.1015.png 1464419894.1016.png 1464419894.1017.png 1464419894.1018.png 1464419894.1019.png 1464419894.1020.png 1464419894.1022.png 1464419894.1023.png 1464419894.1024.png 1464419894.1025.png 1464419894.1026.png 1464419894.1027.png 1464419894.1028.png 1464419894.1029.png 1464419894.1030.png 1464419894.1031.png 1464419894.1033.png 1464419894.1034.png 1464419894.1035.png 1464419894.1036.png 1464419894.1037.png 1464419894.1038.png 1464419894.1039.png 1464419894.1040.png 1464419894.1041.png 1464419894.1042.png 1464419894.1044.png 1464419894.1045.png 1464419894.1046.png 1464419894.1047.png 1464419894.1048.png 1464419894.1049.png 1464419894.1050.png 1464419894.1051.png
 
A
B
C
D
E
DDR_A_D[0..63]
DDR_A_MA[0..15]
DDR_A_DM[0..7]
DDR_A_D[0..63]
<7,8>
DDR_A_MA[0..15]
<7,8>
DDR_A_DM[0..7]
<7,8>
U1E
U1E
DDR_A_MA0
DDR_A_D0
R17
B14
M_ADD0
M_DATA0
DDR_A_MA1
H19
A15
DDR_A_D1
M_ADD1
M_DATA1
DDR_A_MA2
DDR_A_MA3
J17
A17
DDR_A_D2
M_ADD2
M_DATA2
DDR_A_D3
H18
D18
M_ADD3
M_DATA3
DDR_A_MA4
H17
A14
DDR_A_D4
M_ADD4
M_DATA4
DDR_A_MA5
G17
C14
DDR_A_D5
M_ADD5
M_DATA5
DDR_A_MA6
DDR_A_D6
DDR_A_D7
H15
C16
M_ADD6
M_DATA6
DDR_A_MA7
G18
D16
M_ADD7
M_DATA7
4
DDR_A_MA8
4
F19
M_ADD8
DDR_A_MA9
E19
C18
DDR_A_D8
M_ADD9
M_DATA8
DDR_A_MA10
T19
A19
DDR_A_D9
M_ADD10
M_DATA9
DDR_A_MA11
DDR_A_D10
F17
B21
M_ADD11
M_DATA10
DDR_A_MA12
DDR_A_MA14
E18
D20
DDR_A_D11
M_ADD12
M_DATA11
DDR_A_MA13
DDR_A_D12
W17
A18
M_ADD13
M_DATA12
E16
B18
DDR_A_D13
M_ADD14
M_DATA13
DDR_A_MA15
G15
A21
DDR_A_D14
DDR_A_D15
M_ADD15
M_DATA14
8/22 Delete C11~C18 (No VGA)
C20
M_DATA15
R18
<7,8>
DDR_A_BS0
M_BANK0
DDR_A_D16
DDR_A_D17
T18
C23
<7,8>
DDR_A_BS1
M_BANK1
M_DATA16
F16
D23
9/6 Change PCI-E from FCH to APU
<7,8>
DDR_A_BS2
M_BANK2
M_DATA17
F23
DDR_A_D18
M_DATA18
DDR_A_DM0
DDR_A_D19
D15
F22
M_DM0
M_DATA19
DDR_A_DM1
B19
C22
DDR_A_D20
9/6 Update PCI-E port List
M_DM1
M_DATA20
DDR_A_DM2
DDR_A_D21
D21
D22
M_DM2
M_DATA21
DDR_A_DM3
H22
F20
DDR_A_D22
DDR_A_D23
9/15 Change PCI-E from APU to FCH
M_DM3
M_DATA22
DDR_A_DM4
P23
F21
M_DM4
M_DATA23
DDR_A_DM5
V23
M_DM5
DDR_A_DM6
AB20
H21
DDR_A_D24
M_DM6
M_DATA24
DDR_A_DM7
DDR_A_D25
AA16
H23
M_DM7
M_DATA25
U1A
U1A
K22
DDR_A_D26
M_DATA26
DDR_A_DQS0
DDR_A_DQS#0
A16
K21
DDR_A_D27
AA6
AB6
<7,8>
DDR_A_DQS0
M_DQS_H0
M_DATA27
P_GPP_RXP0
P_GPP_TXP0
DDR_A_D28
B16
G23
Y6
AC6
<7,8>
DDR_A_DQS#0
M_DQS_L0
M_DATA28
P_GPP_RXN0
P_GPP_TXN0
DDR_A_DQS1
DDR_A_DQS#1
B20
H20
DDR_A_D29
<7,8>
DDR_A_DQS1
M_DQS_H1
M_DATA29
A20
K20
DDR_A_D30
DDR_A_D31
AB4
AB3
<7,8>
DDR_A_DQS#1
M_DQS_L1
M_DATA30
P_GPP_RXP1
P_GPP_TXP1
DDR_A_DQS2
DDR_A_DQS#2
E23
K23
AC4
AC3
<7,8>
DDR_A_DQS2
M_DQS_H2
M_DATA31
P_GPP_RXN1
P_GPP_TXN1
E22
<7,8>
DDR_A_DQS#2
M_DQS_L2
DDR_A_DQS3
DDR_A_DQS#3
DDR_A_D32
J22
N23
AA1
Y1
<7,8>
DDR_A_DQS3
M_DQS_H3
M_DATA32
P_GPP_RXP2
P_GPP_TXP2
J23
P21
DDR_A_D33
AA2
Y2
<7,8>
DDR_A_DQS#3
M_DQS_L3
M_DATA33
P_GPP_RXN2
P_GPP_TXN2
DDR_A_DQS4
DDR_A_DQS#4
R22
T20
DDR_A_D34
M_DQS_H4
M_DATA34
<7,8>
DDR_A_DQS4
DDR_A_D35
P22
T23
Y4
V3
<7,8>
DDR_A_DQS#4
M_DQS_L4
M_DATA35
P_GPP_RXP3
P_GPP_TXP3
3
DDR_A_DQS5
DDR_A_DQS#5
W22
M20
DDR_A_D36
Y3
V4
3
<7,8>
DDR_A_DQS5
M_DQS_H5
M_DATA36
P_GPP_RXN3
P_GPP_TXN3
DDR_A_D37
V22
P20
<7,8>
DDR_A_DQS#5
M_DQS_L5
M_DATA37
DDR_A_DQS6
DDR_A_DQS#6
AC20
R23
DDR_A_D38
DDR_A_D39
1
2
P_ZVDD_10
Y14
AA14
P_ZVSS
R54
R54
1
2
1.27K_0402_1%
1.27K_0402_1%
+1.05VS
<7,8>
DDR_A_DQS6
M_DQS_H6
M_DATA38
P_ZVDD_10
P_ZVSS
AC21
T22
R53
R53
2K_0402_1%
2K_0402_1%
M_DQS_L6
M_DATA39
<7,8>
DDR_A_DQS#6
DDR_A_DQS7
DDR_A_DQS#7
Less than 1"
AB16
<7,8>
DDR_A_DQS7
M_DQS_H7
AC16
V20
DDR_A_D40
DDR_A_D41
Less than 1"
<7,8>
DDR_A_DQS#7
M_DQS_L7
M_DATA40
UMI_TX0P_C
UMI_TX0N_C
UMI_TX1P_C
UMI_TX1N_C
C19
C19
.1U_0402_16V7K
.1U_0402_16V7K
V21
AA12
AB12
1
2
<12>
UMI_RX0P
UMI_TX0P
<12>
M_DATA41
P_UMI_RXP0
P_UMI_TXP0
C20
C20
.1U_0402_16V7K
.1U_0402_16V7K
DDR_A_CLK0
DDR_A_CLK1
M17
Y23
DDR_A_D42
Y12
AC12
1
2
<12>
UMI_RX0N
<7>
DDR_A_CLK0
M_CLK_H0
M_DATA42
P_UMI_RXN0
P_UMI_TXN0
UMI_TX0N
<12>
DDR_A_CLK#0
M16
Y22
DDR_A_D43
<7>
DDR_A_CLK#0
M_CLK_L0
M_DATA43
DDR_A_D44
C21
C21
.1U_0402_16V7K
.1U_0402_16V7K
M19
T21
AA10
AC11
1
2
<12>
UMI_RX1P
<7>
DDR_A_CLK1
M_CLK_H1
M_DATA44
P_UMI_RXP1
P_UMI_TXP1
UMI_TX1P
<12>
DDR_A_CLK#1
M18
U23
DDR_A_D45
Y10
AB11
C22
C22
1
2
.1U_0402_16V7K
.1U_0402_16V7K
<12>
UMI_RX1N
<7>
DDR_A_CLK#1
M_CLK_L1
M_DATA45
P_UMI_RXN1
P_UMI_TXN1
UMI_TX1N
<12>
DDR_B_CLK2
DDR_B_CLK3
DDR_A_D46
N18
W23
<8>
DDR_B_CLK2
M_CLK_H2
M_DATA46
C23
C23
.1U_0402_16V7K
.1U_0402_16V7K
DDR_B_CLK#2
N19
Y21
DDR_A_D47
AB10
AA8
UMI_TX2P_C
UMI_TX2N_C
UMI_TX3P_C
UMI_TX3N_C
1
2
<12>
UMI_RX2P
<8>
DDR_B_CLK#2
M_CLK_L2
M_DATA47
P_UMI_RXP2
P_UMI_TXP2
UMI_TX2P
<12>
L18
AC10
Y8
C24
C24
1
2
.1U_0402_16V7K
.1U_0402_16V7K
<8>
DDR_B_CLK3
M_CLK_H3
<12>
UMI_RX2N
P_UMI_RXN2
P_UMI_TXN2
UMI_TX2N
<12>
DDR_B_CLK#3
DDR_A_D48
L17
Y20
<8>
DDR_B_CLK#3
M_CLK_L3
M_DATA48
AB22
DDR_A_D49
AC7
AB8
C25
C25
1
2
.1U_0402_16V7K
.1U_0402_16V7K
<12>
UMI_RX3P
M_DATA49
P_UMI_RXP3
P_UMI_TXP3
UMI_TX3P
<12>
DDR_RST#
DDR_A_D50
C26
C26
.1U_0402_16V7K
.1U_0402_16V7K
L23
AC19
AB7
AC8
1
2
<7,8>
DDR_RST#
<12>
UMI_RX3N
UMI_TX3N
<12>
M_RESET_L
M_DATA50
P_UMI_RXN3
P_UMI_TXN3
DDR_EVENT#
N17
AA18
DDR_A_D51
<7,8>
DDR_EVENT#
M_EVENT_L
M_DATA51
AA23
DDR_A_D52
S IC ONTARIO CMC50AFPB22GT 1G BGA ABO!
S IC ONTARIO CMC50AFPB22GT 1G BGA ABO!
M_DATA52
DDR_A_D53
AA20
M_DATA53
DDR_CKE0
DDR_CKE1
F15
AB19
DDR_A_D54
<7,8>
DDR_CKE0
M_CKE0
M_DATA54
E15
Y18
DDR_A_D55
<7,8>
DDR_CKE1
M_CKE1
M_DATA55
AC17
DDR_A_D56
DDR_A_D58
M_DATA56
DDR_A_D57
Y16
M_DATA57
DDR_A_ODT0
W19
AB14
<7>
DDR_A_ODT0
M0_ODT0
M_DATA58
DDR_A_ODT1
V15
AC14
DDR_A_D59
<7>
DDR_A_ODT1
M0_ODT1
M_DATA59
DDR_B_ODT0
DDR_A_D60
U19
AC18
<8>
DDR_B_ODT0
M1_ODT0
M_DATA60
DDR_B_ODT1
W15
AB18
DDR_A_D61
<8>
DDR_B_ODT1
M1_ODT1
M_DATA61
DDR_A_D62
DDR_A_D63
AB15
M_DATA62
DDR_CS0_DIMMA#
T17
AC15
<7>
DDR_CS0_DIMMA#
M0_CS_L0
M_DATA63
DDR_CS1_DIMMA#
W16
<7>
DDR_CS1_DIMMA#
M0_CS_L1
2
DDR_CS0_DIMMB#
2
U17
<8>
DDR_CS0_DIMMB#
M1_CS_L0
DDR_CS1_DIMMB#
V16
M23
+MEM_VREF
<8>
DDR_CS1_DIMMB#
M1_CS_L1
M_VREF
DDR_A_RAS#
U18
<7,8>
DDR_A_RAS#
M_RAS_L
DDR_A_CAS#
V19
R55
R55
<7,8>
DDR_A_CAS#
M_CAS_L
DDR_A_WE#
+M_ZVDDIO
V17
M22
2
1
<7,8>
DDR_A_WE#
+1.5V
M_WE_L
M_ZVDDIO_MEM_S
S IC ONTARIO CMC50AFPB22GT 1G BGA ABO!
S IC ONTARIO CMC50AFPB22GT 1G BGA ABO!
39.2_0402_1%
39.2_0402_1%
9/11 Delete DDR Signal link to JDIMM2
+1.5V
Reserve C439 for DDR_EVENT#
Michael 2010/11/18
+1.5V
R56
1K_0402_1%
R57
R57
1
2
DDR_EVENT#
1K_0402_5%
1K_0402_5%
+MEM_VREF
@
@
1
1
1
R58
1K_0402_1%
C27
1000P_0402_50V7K
C28
C28
1
C439
100P_0402_50V8J
C439
100P_0402_50V8J
1
0.1U_0402_16V4Z
0.1U_0402_16V4Z
2
2
2
Place within 1000 mils to APU
20100526
Compal Electronics, Inc.
Security Classification
Security Classification
Security Classification
Compal Secret Data
Compal Secret Data
Compal Secret Data
2010/11/09
2010/11/09
2010/11/09
2012/11/09
2012/11/09
2012/11/09
Title
Title
Title
Issued Date
Issued Date
Issued Date
Deciphered Date
Deciphered Date
Deciphered Date
FT1 DDRIII/UMI/PCIE
FT1 DDRIII/UMI/PCIE
FT1 DDRIII/UMI/PCIE
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Size
Size
Size
Document Number
Document Number
Document Number
Rev
Rev
Rev
P1VE6 Schematics
P1VE6 Schematics
P1VE6 Schematics
Custom
Custom
Custom
1.0
1.0
1.0
Date:
Date:
Date:
Thursday, March 17, 2011
Thursday, March 17, 2011
Thursday, March 17, 2011
Sheet
Sheet
Sheet
5
5
5
of
of
of
37
37
37
A
B
C
D
E
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