Acer Aspire 4240_4540_Compal_LA-5521P_NBLG0_Rev0.2.pdf
(
1790 KB
)
Pobierz
A
B
C
D
E
1
1
Compal Confidential
2
2
NBLG0 Schematics Document
AMD Tigris (JV40-TR) : Caspian Processor with RS880M/SB710/M92-M2 XT
2009-06-04
3
3
REV:0.2
4
4
Compal Electronics, Inc.
Compal Electronics, Inc.
Compal Electronics, Inc.
Security Classification
Security Classification
Security Classification
Compal Secret Data
Compal Secret Data
Compal Secret Data
2008/10/06
2008/10/06
2008/10/06
2009/10/06
2009/10/06
2009/10/06
Title
Title
Title
Issued Date
Issued Date
Issued Date
Deciphered Date
Deciphered Date
Deciphered Date
Cover Page
Cover Page
Cover Page
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Size
Size
Size
Document Number
Document Number
Document Number
Rev
Rev
Rev
NBLG0 LA-5521P
NBLG0 LA-5521P
NBLG0 LA-5521P
B
B
B
0.1
0.1
0.1
Date:
Date:
Date:
Thursday, June 04, 2009
Thursday, June 04, 2009
Thursday, June 04, 2009
Sheet
Sheet
Sheet
1
1
1
of
of
of
58
58
58
A
B
C
D
E
A
B
C
D
E
Tigris
Compal Confidential
AMD S1G3 Processor
VRAM 512MB
64M16 x 4
Memory BUS(DDRII)
Model Name : NBLG0
200pin DDRII-SO-DIMM X2
uPGA-638 Package
Fan Control
Dual Channel
page 19, 20
page 8,9
PowerXpress (MUX)
BANK 0, 1, 2, 3
page 44
page 4,5,6,7
Caspian
1.8V DDRII 800 (667)
DDR2 500MHz
LCD (LED BL)
MUX
(1:2)
1
1
Hyper Transport Link
16 x 16
5 in 1 socket
page 24
ATI M92-M2 XT
page 33
PCI-Express 16x
uFCBGA-962
CRT
MUX
(1:2)
Page 14,15,16,17,18,21,22
Gen2
Thermal Sensor
ADM1032
Clock Generator
SLG8SP626VTR
ATI RS880M
page 26
Card Reader
RTS5159
page 6
page 23
HDMI Conn.
uFCBGA-528
page 33
page 25
PCI-Express 1x
option1
page 10,11,12,13
page 36,37
page 27
page 37
page 36
page 36
option2
USB
conn
X 2
Finger
printer
AES1610
Mini
card
(WL)X1
CMOS
Camera
Bluetooth
Conn
A link Express2
MINI Card x1
WLAN
page 36
LAN(GbE)
Card Reader
JMB385
Atheros AR8131
page 34
page 33
USB port 0,6
USB
USB port 3
USB port 12
USB port 13
USB port 8
USB port 4
port 2
port 3
port 4
ATI SB710
2
3.3V 48MHz
2
RJ45
page 35
5 in 1 socket
3.3V 24.576MHz/48Mhz
HD Audio
page 33
uFCBGA-528
USB port 1
page 27,28,29,30,31
S-ATA
MDC 1.5
Conn
HDA Codec
ALC888
Digital MIC
page 41
page 42
page 42
LPC BUS
SATA HDD
Conn.
port 0
CDROM
Conn.
page 32
ESATA
Conn.
LED
page 40
page 32
page 37
port 1
port 2
Audio AMP
RTC CKT.
page 26
page 43
ENE KB926
page 38
3
3
Phone Jack x3
LID SW / MEDIA/B
page 43
Int.KBD
Touch Pad
page 39
page 39
page 39
Power On/Off CKT.
EC I/O Buffer
BIOS
page 41
page 38
page 39
DC/DC Interface CKT.
page 45
Power Circuit
page 46,47,48,49,50,51
52,53,54
4
4
Compal Electronics, Inc.
Compal Electronics, Inc.
Compal Electronics, Inc.
Security Classification
Security Classification
Security Classification
Compal Secret Data
Compal Secret Data
Compal Secret Data
2008/10/06
2008/10/06
2008/10/06
2009/10/06
2009/10/06
2009/10/06
Title
Title
Title
Issued Date
Issued Date
Issued Date
Deciphered Date
Deciphered Date
Deciphered Date
Block Diagrams
Block Diagrams
Block Diagrams
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Size
Size
Size
Document Number
Document Number
Document Number
Rev
Rev
Rev
NBLG0 LA-5521P
NBLG0 LA-5521P
NBLG0 LA-5521P
B
B
B
0.1
0.1
0.1
Date:
Date:
Date:
Sunday, April 12, 2009
Sunday, April 12, 2009
Sunday, April 12, 2009
Sheet
Sheet
Sheet
2
2
2
of
of
of
58
58
58
A
B
C
D
E
A
B
C
D
E
SIGNAL
STATE
SLP_S1# SLP_S3# SLP_S4# SLP_S5# +VALW
+V
+VS
Clock
Voltage Rails
Full ON
HIGH
HIGH
HIGH
HIGH
HIGH
ON
ON
ON
ON
ON
ON
LOW
HIGH
HIGH
ON
LOW
Power Plane
Description
S1
S3
S5
S1(Power On Suspend)
S3 (Suspend to RAM)
VIN
B+
Adapter power supply (19V)
AC or battery power rail for power circuit.
Core voltage for CPU (0.7-1.2V)
N/A
N/A
N/A
N/A
LOW
LOW
HIGH
HIGH
ON
ON
OFF
OFF
N/A
N/A
S4 (Suspend to Disk)
S5 (Soft OFF)
LOW
LOW
LOW
HIGH
ON
OFF
OFF
OFF
OFF
OFF
OFF
1
+CPU_CORE_0
ON
OFF
OFF
1
+CPU_CORE_1
Core voltage for CPU (0.7-1.2V)
ON
OFF
OFF
LOW
LOW
LOW
LOW
ON
+CPU_CORE_NB
Voltage for On-die Northbridge of CPU(0.8-1.1V)
ON
OFF
OFF
+0.9V
0.9V switched power rail for DDR terminator
ON
ON
OFF
Board ID / SKU ID Table for AD channel
Vcc
+1.1VS
1.1V switched power rail for NB VDDC & VGA
ON
OFF
OFF
3.3V +/- 5%
100K +/- 5%
+1.2V_HT
1.2V switched power rail
ON
OFF
OFF
Ra/Rc/Re
Board ID
+VGA_CORE
0.95-1.2V switched power rail
ON
OFF
OFF
Rb / Rd / Rf
V
min
V
typ
V
AD_BID
max
+1.5VS
1.5V power rail for PCIE Card
ON
OFF
OFF
AD_BID
AD_BID
+1.8V
1.8V power rail for CPU VDDIO and DDR
ON
ON
OFF
0
1
2
3
0
8.2K +/- 5%
0 V
0.216 V
0 V
0 V
+1.8VS
1.8V switched power rail
ON
OFF
OFF
0.250 V
0.289 V
+2.5VS
2.5V for CPU_VDDA
ON
OFF
OFF
18K +/- 5%
33K +/- 5%
56K +/- 5%
100K +/- 5%
200K +/- 5%
0.436 V
0.712 V
0.503 V
0.819 V
0.538 V
0.875 V
+3VALW
3.3V always on power rail
ON
ON
ON*
+3V_LAN
3.3V power rail for LAN
ON
ON
ON
4
5
6
7
1.036 V
1.453 V
1.185 V
1.264 V
+3VS
+5VALW
3.3V switched power rail
ON
OFF
OFF
1.650 V
1.759 V
5V always on power rail
ON
ON
ON*
1.935 V
2.500 V
2.200 V
3.300 V
2.341 V
+5VS
5V switched power rail
ON
OFF
OFF
NC
3.300 V
2
+VSB
VSB always on power rail
ON
ON
ON
ON*
ON
2
+RTCVCC
RTC power
ON
BOARD ID Table
BTO Option Table
Note : ON* means that this power plane is ON only with AC power available, otherwise it is OFF.
Board ID
0
1
2
3
4
5
6
7
PCB Revision
BTO Item
BOM Structure
External PCI Devices
Device
Discrete
UMA
VGA@
IDSEL#
REQ#/GNT#
Interrupts
0.1(DVT)
UMA@
0.2(PVT)
1.0(MP)
M92-M2 XT
VRAM STRAP
M92@
VRAM@
LAN 8121
8121@
LAN 8131
8131@
HDT debug
HDT@
JMB385 CR
JMB385@
RTS5159 CR
RTS5159@
FOR PUMA
PUMA@
EC SM Bus1 address
EC SM Bus2 address
FOR TIGRIS
TIGRIS@
FOR TEST
UB@
3
3
Device
Address
HEX
Device
Address
HEX
98H
9AH
Smart Battery
16H
ADI ADM1032 (CPU)
SB700
SB700
RS780MN
DISPLAY OUTPUT
0001 011X b
1001 100X b
PX_GPIO0
PX_GPIO1
PX_GPIO2
GMT G781-1 (GPU)
1001 101X b
SB-Temp Sensor
9CH
Function Description
dGPU_Reset
PX Mode Switch
dGPU_PWR_Enable
IGP only mode
X
X
X
PowerXpress mode
H : Enable
H : Enable
L : iGPU(DC) / H : dGPU(AC)
LVDS / CRT
SB700
SM Bus 0 address
SB700
SM Bus 1 address
KB926
PX_GPIO1
PX_GPIO2
PX_+3VS
PX_+1.8VS
Enable +1.8VS_PX
PX_+VGA_CORE
PX_GPIO2_NB
Device
Address
HEX
Device
Address
Function Description
Enable +1.1VS_PX
PX MODE SWITCH
Enable +3VS_DELAY
Enable +VGA_CORE
Trigger from SB
New card
IGP only mode
X
H : Enable
X
X
X
X
X
Clock Generator
(SILEGO SLG8SP626)
1101 001Xb
D2
PowerXpress mode
Reserved
H : Enable
H : Enable
H : Enable
Reserved
DDR DIMM1
1001 000Xb
90
94
KB926
DDR DIMM2
1001 010Xb
PX_GPIO1_SB
Mini card
Function Description
Trigger from SB to Enable (PX_GPIO1/PX_+3VS/PX_+1.8VS/PX_+VGA_CORE)
4
4
IGP only mode
X
H : Enable
PowerXpress mode
Compal Electronics, Inc.
Compal Electronics, Inc.
Compal Electronics, Inc.
Security Classification
Security Classification
Security Classification
Compal Secret Data
Compal Secret Data
Compal Secret Data
2008/10/06
2008/10/06
2008/10/06
2009/10/06
2009/10/06
2009/10/06
Title
Title
Title
Issued Date
Issued Date
Issued Date
Deciphered Date
Deciphered Date
Deciphered Date
Notes List
Notes List
Notes List
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Size
Size
Size
Document Number
Document Number
Document Number
Rev
Rev
Rev
KBLG0 LA-4921P
KBLG0 LA-4921P
KBLG0 LA-4921P
B
B
B
0.1
0.1
0.1
Date:
Date:
Date:
Thursday, June 04, 2009
Thursday, June 04, 2009
Thursday, June 04, 2009
Sheet
Sheet
Sheet
3
3
3
of
of
of
58
58
58
A
B
C
D
E
A
B
C
D
E
1
1
VLDT CAP.
+1.2V_HT
250 mil
1
1
1
1
1
1
C727
4.7U_0805_10V4Z
C727
4.7U_0805_10V4Z
C666
4.7U_0805_10V4Z
C666
4.7U_0805_10V4Z
C725
0.22U_0603_16V4Z
C726
0.22U_0603_16V4Z
C722
180P_0402_50V8J
C668
180P_0402_50V8J
H_CADIP[0..15]
H_CADOP[0..15]
H_CADON[0..15]
10
H_CADIP[0..15]
H_CADOP[0..15]
10
2
2
2
2
2
2
H_CADIN[0..15]
10
H_CADIN[0..15]
H_CADON[0..15]
10
PUMA@
PUMA@
PUMA@
PUMA@
Change as 10U
for Tigris
Near CPU Socket
Change as 10U
for Tigris
+1.2V_HT
+1.2V_HT
JCPU1A
JCPU1A
PUMA@
PUMA@
2
2
D1
HT LINK
HT LINK
AE2
1
2
VLDT_A0
VLDT_B0
VLDT=1.5A
C664
C664
4.7U_0805_10V4Z
4.7U_0805_10V4Z
D2
AE3
VLDT_A1
VLDT_B1
D3
AE4
VLDT_A2
VLDT_B2
D4
AE5
VLDT_A3
VLDT_B3
H_CADIP0
H_CADOP0
E3
AD1
L0_CADIN_H0
L0_CADOUT_H0
H_CADIN0
H_CADON0
E2
AC1
L0_CADIN_L0
L0_CADOUT_L0
H_CADIP1
H_CADOP1
H_CADOP2
E1
AC2
L0_CADIN_H1
L0_CADOUT_H1
H_CADIN1
F1
AC3
H_CADON1
L0_CADIN_L1
L0_CADOUT_L1
H_CADIP2
G3
AB1
L0_CADIN_H2
L0_CADOUT_H2
H_CADIN2
G2
AA1
H_CADON2
H_CADON3
L0_CADIN_L2
L0_CADOUT_L2
H_CADIP3
H_CADOP3
G1
AA2
L0_CADIN_H3
L0_CADOUT_H3
H_CADIN3
H_CADIP4
H1
AA3
L0_CADIN_L3
L0_CADOUT_L3
H_CADOP4
H_CADOP5
J1
W2
L0_CADIN_H4
L0_CADOUT_H4
H_CADIN4
H_CADIP5
H_CADON4
K1
W3
L0_CADIN_L4
L0_CADOUT_L4
L3
V1
L0_CADIN_H5
L0_CADOUT_H5
H_CADIN5
H_CADON5
L2
U1
L0_CADIN_L5
L0_CADOUT_L5
H_CADIP6
H_CADIP7
H_CADOP6
L1
U2
L0_CADIN_H6
L0_CADOUT_H6
H_CADIN6
H_CADON6
M1
U3
L0_CADIN_L6
L0_CADOUT_L6
H_CADOP7
N3
T1
L0_CADIN_H7
L0_CADOUT_H7
H_CADIN7
H_CADON7
N2
R1
L0_CADIN_L7
L0_CADOUT_L7
H_CADIP8
H_CADOP8
E5
AD4
L0_CADIN_H8
L0_CADOUT_H8
H_CADIN8
H_CADON8
F5
AD3
L0_CADIN_L8
L0_CADOUT_L8
H_CADIP9
F3
AD5
H_CADOP9
H_CADOP10
L0_CADIN_H9
L0_CADOUT_H9
H_CADIN9
H_CADON9
F4
AC5
L0_CADIN_L9
L0_CADOUT_L9
H_CADIP10
G5
AB4
L0_CADIN_H10
L0_CADOUT_H10
H_CADIN10
H_CADON10
H5
AB3
L0_CADIN_L10
L0_CADOUT_L10
H_CADIP11
H_CADOP11
H3
AB5
L0_CADIN_H11
L0_CADOUT_H11
H_CADIN11
H_CADON11
H4
AA5
L0_CADIN_L11
L0_CADOUT_L11
H_CADIP12
H_CADOP12
K3
Y5
L0_CADIN_H12
L0_CADOUT_H12
H_CADIN12
H_CADON12
K4
W5
L0_CADIN_L12
L0_CADOUT_L12
H_CADIP13
H_CADOP13
L5
V4
L0_CADIN_H13
L0_CADOUT_H13
3
H_CADIN13
H_CADON13
3
M5
V3
L0_CADIN_L13
L0_CADOUT_L13
H_CADIP14
H_CADOP14
M3
V5
L0_CADIN_H14
L0_CADOUT_H14
H_CADIN14
H_CADON14
M4
U5
L0_CADIN_L14
L0_CADOUT_L14
H_CADIP15
H_CADOP15
N5
T4
L0_CADIN_H15
L0_CADOUT_H15
H_CADIN15
P5
T3
H_CADON15
L0_CADIN_L15
L0_CADOUT_L15
J3
Y1
10
H_CLKIP0
H_CLKOP0
10
L0_CLKIN_H0
L0_CLKOUT_H0
J2
W1
10
H_CLKIN0
L0_CLKIN_L0
L0_CLKOUT_L0
H_CLKON0
10
J5
Y4
10
H_CLKIP1
H_CLKOP1
10
L0_CLKIN_H1
L0_CLKOUT_H1
K5
Y3
10
H_CLKIN1
L0_CLKIN_L1
L0_CLKOUT_L1
H_CLKON1
10
N1
R2
10
H_CTLIP0
L0_CTLIN_H0
L0_CTLOUT_H0
H_CTLOP0
10
P1
R3
10
H_CTLIN0
H_CTLON0
10
L0_CTLIN_L0
L0_CTLOUT_L0
P3
T5
10
H_CTLIP1
L0_CTLIN_H1
L0_CTLOUT_H1
H_CTLOP1
10
P4
R5
10
H_CTLIN1
H_CTLON1
10
L0_CTLIN_L1
L0_CTLOUT_L1
conn@
conn@
6090022100G_B
6090022100G_B
4
4
Compal Electronics, Inc.
Compal Electronics, Inc.
Compal Electronics, Inc.
Security Classification
Security Classification
Security Classification
Compal Secret Data
Compal Secret Data
Compal Secret Data
2008/10/06
2008/10/06
2008/10/06
2009/10/06
2009/10/06
2009/10/06
Title
Title
Title
Issued Date
Issued Date
Issued Date
Deciphered Date
Deciphered Date
Deciphered Date
AMD CPU S1G3 HT I/F
AMD CPU S1G3 HT I/F
AMD CPU S1G3 HT I/F
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Size
Size
Size
Document Number
Document Number
Document Number
Rev
Rev
Rev
NBLG0 LA-5521P
NBLG0 LA-5521P
NBLG0 LA-5521P
Custom
Custom
Custom
0.1
0.1
0.1
Date:
Date:
Date:
Thursday, June 04, 2009
Thursday, June 04, 2009
Thursday, June 04, 2009
Sheet
Sheet
Sheet
4
4
4
of
of
of
58
58
58
A
B
C
D
E
A
B
C
D
E
Processor DDR2 Memory Interface
PLACE CLOSE TO PROCESSOR
WITHIN 1.5 INCH
JCPU1C
JCPU1C
9
DDRB_SDQ[63..0]
MEM:DATA
MEM:DATA
DDRA_SDQ[63..0]
8
DDRA_CLK0
DDRB_SDQ0
C11
G12
DDRA_SDQ0
DDRA_SDQ1
DDRA_SDQ2
MB_DATA0
MA_DATA0
1
+1.8V
DDRB_SDQ1
DDRB_SDQ2
DDRB_SDQ3
DDRB_SDQ4
DDRB_SDQ5
DDRB_SDQ6
DDRB_SDQ7
DDRB_SDQ8
DDRB_SDQ9
DDRB_SDQ10
DDRB_SDQ11
DDRB_SDQ12
DDRB_SDQ13
DDRB_SDQ14
DDRB_SDQ15
DDRB_SDQ16
DDRB_SDQ17
DDRB_SDQ18
DDRB_SDQ19
DDRB_SDQ20
DDRB_SDQ21
DDRB_SDQ22
DDRB_SDQ23
DDRB_SDQ24
DDRB_SDQ25
DDRB_SDQ26
DDRB_SDQ27
DDRB_SDQ28
DDRB_SDQ29
DDRB_SDQ30
DDRB_SDQ31
DDRB_SDQ32
DDRB_SDQ33
DDRB_SDQ34
DDRB_SDQ35
DDRB_SDQ36
DDRB_SDQ37
DDRB_SDQ38
DDRB_SDQ39
DDRB_SDQ40
DDRB_SDQ41
DDRB_SDQ42
DDRB_SDQ43
DDRB_SDQ44
DDRB_SDQ45
DDRB_SDQ46
DDRB_SDQ47
DDRB_SDQ48
DDRB_SDQ49
DDRB_SDQ50
DDRB_SDQ51
DDRB_SDQ52
DDRB_SDQ53
DDRB_SDQ54
DDRB_SDQ55
DDRB_SDQ56
DDRB_SDQ57
DDRB_SDQ58
DDRB_SDQ59
DDRB_SDQ60
DDRB_SDQ61
DDRB_SDQ62
DDRB_SDQ63
1
A11
F12
1
MB_DATA1
MA_DATA1
A14
H14
MB_DATA2
MA_DATA2
C379
1.5P_0402_50V9C
DDRA_SDQ3
DDRA_SDQ4
B14
G14
MB_DATA3
MA_DATA3
G11
H11
2
MB_DATA4
MA_DATA4
R78
1K_0402_1%
DDRA_CLK0#
DDRA_SDQ5
DDRA_SDQ6
DDRA_SDQ7
DDRA_SDQ8
DDRA_SDQ9
DDRA_SDQ10
DDRA_SDQ11
DDRA_SDQ12
DDRA_SDQ13
DDRA_SDQ14
DDRA_SDQ15
DDRA_SDQ16
DDRA_SDQ17
DDRA_SDQ18
DDRA_SDQ19
DDRA_SDQ20
DDRA_SDQ21
DDRA_SDQ22
DDRA_SDQ23
DDRA_SDQ24
DDRA_SDQ25
DDRA_SDQ26
DDRA_SDQ27
DDRA_SDQ28
DDRA_SDQ29
DDRA_SDQ30
DDRA_SDQ31
DDRA_SDQ32
DDRA_SDQ33
DDRA_SDQ34
DDRA_SDQ35
DDRA_SDQ36
DDRA_SDQ37
DDRA_SDQ38
DDRA_SDQ39
DDRA_SDQ40
DDRA_SDQ41
DDRA_SDQ42
DDRA_SDQ43
DDRA_SDQ44
DDRA_SDQ45
DDRA_SDQ46
DDRA_SDQ47
DDRA_SDQ48
DDRA_SDQ49
DDRA_SDQ50
DDRA_SDQ51
DDRA_SDQ52
DDRA_SDQ53
DDRA_SDQ54
DDRA_SDQ55
DDRA_SDQ56
DDRA_SDQ57
DDRA_SDQ58
DDRA_SDQ59
DDRA_SDQ60
DDRA_SDQ61
DDRA_SDQ62
DDRA_SDQ63
E11
H12
MB_DATA5
MA_DATA5
D12
C13
MB_DATA6
MA_DATA6
DDRA_CLK1
A13
E13
MB_DATA7
MA_DATA7
1
A15
H15
MB_DATA8
MA_DATA8
+
M
CH_REF
A16
E15
MB_DATA9
MA_DATA9
C111
1.5P_0402_50V9C
A19
E17
MB_DATA10
MA_DATA10
A20
H17
1
1
MB_DATA11
MA_DATA11
2
R79
1K_0402_1%
DDRA_CLK1#
C14
E14
MB_DATA12
MA_DATA12
D14
F14
MB_DATA13
MA_DATA13
C18
C17
2
2
MB_DATA14
MA_DATA14
DDRB_CLK0
D18
G17
MB_DATA15
MA_DATA15
D20
G18
1
MB_DATA16
MA_DATA16
A21
C19
MB_DATA17
MA_DATA17
C380
1.5P_0402_50V9C
D24
D22
MB_DATA18
MA_DATA18
C25
E20
2
MB_DATA19
MA_DATA19
DDRB_CLK0#
DDRB_CLK1
B20
E18
MB_DATA20
MA_DATA20
C20
F18
MB_DATA21
MA_DATA21
B24
B22
MB_DATA22
MA_DATA22
1
C24
C23
MB_DATA23
MA_DATA23
E23
F20
MB_DATA24
MA_DATA24
C112
1.5P_0402_50V9C
E24
F22
MB_DATA25
MA_DATA25
G25
H24
MB_DATA26
MA_DATA26
2
DDRB_CLK1#
G26
J19
MB_DATA27
MA_DATA27
C26
E21
MB_DATA28
MA_DATA28
D26
E22
MB_DATA29
MA_DATA29
G23
H20
MB_DATA30
MA_DATA30
+0.9V
+0.9V
G24
H22
MB_DATA31
MA_DATA31
JCPU1B
JCPU1B
A
A24
Y24
MB_DATA32
MA_DATA32
2
VTT=0.75A
2
A
A23
AB24
MB_DATA33
MA_DATA33
D10
W10
A
D24
AB22
VTT1
VTT5
MB_DATA34
MA_DATA34
Place them close to CPU within 1"
C10
MEM:CMD/CTRL/CLK
MEM:CMD/CTRL/CLK
AC10
A
E24
AA21
VTT2
VTT6
MB_DATA35
MA_DATA35
B10
AB10
A
A26
W22
VTT3
VTT7
MB_DATA36
MA_DATA36
AD10
AA10
A
A25
W21
VTT4
VTT8
MB_DATA37
MA_DATA37
R77
R77
39.2_0402_1%
39.2_0402_1%
A10
A
D26
Y22
VTT9
MB_DATA38
MA_DATA38
1
2
A
F10
A
E25
AA22
MEMZP
MB_DATA39
MA_DATA39
VTT_SENSE
1
2
AE10
Y10
A
C22
Y20
+1.8V
MEMZN
VTT_SENSE
PAD
PAD
T4
T4
MB_DATA40
MA_DATA40
R76
R76
39.2_0402_1%
39.2_0402_1%
A
D22
AA20
MB_DATA41
MA_DATA41
+MCH_REF
H16
W17
A
E20
AA18
RSVD_M1
MEMVREF
MB_DATA42
MA_DATA42
A
F20
AB18
MB_DATA43
MA_DATA43
DDRA_ODT0
T19
B18
A
F24
AB21
8
DDRA_ODT0
MA0_ODT0
RSVD_M2
MB_DATA44
MA_DATA44
DDRA_ODT1
V22
A
F23
AD21
8
DDRA_ODT1
MA0_ODT1
MB_DATA45
MA_DATA45
DDRB_ODT0
DDRB_ODT1
U21
W26
A
C20
AD19
MA1_ODT0
MB0_ODT0
DDRB_ODT0
9
MB_DATA46
MA_DATA46
V19
W23
A
D20
Y18
DDRB_ODT1
9
MA1_ODT1
MB0_ODT1
MB_DATA47
MA_DATA47
Y26
A
D18
AD17
MB1_ODT0
MB_DATA48
MA_DATA48
DDRA_SCS0#
T20
A
E18
W16
8
DDRA_SCS0#
MA0_CS_L0
MB_DATA49
MA_DATA49
DDRA_SCS1#
DDRB_SCS0#
DDRB_SCS1#
U19
V26
A
C14
W14
8
DDRA_SCS1#
MA0_CS_L1
MB0_CS_L0
DDRB_SCS0#
9
MB_DATA50
MA_DATA50
U20
W25
A
D14
Y14
DDRB_SCS1#
9
MA1_CS_L0
MB0_CS_L1
MB_DATA51
MA_DATA51
V20
U22
A
F19
Y17
MA1_CS_L1
MB1_CS_L0
MB_DATA52
MA_DATA52
A
C18
AB17
MB_DATA53
MA_DATA53
DDRA_CKE0
DDRA_CKE1
DDRB_CKE0
J22
J25
A
F16
AB15
8
DDRA_CKE0
MA_CKE0
MB_CKE0
DDRB_CKE0
9
MB_DATA54
MA_DATA54
DDRB_CKE1
J20
H26
A
F15
AD15
8
DDRA_CKE1
MA_CKE1
MB_CKE1
DDRB_CKE1
9
MB_DATA55
MA_DATA55
A
F13
AB13
MB_DATA56
MA_DATA56
N19
P22
A
C12
AD13
MA_CLK_H0
MB_CLK_H0
MB_DATA57
MA_DATA57
N20
R22
A
B11
Y12
MA_CLK_L0
MB_CLK_L0
MB_DATA58
MA_DATA58
DDRA_CLK0
DDRA_CLK1
DDRB_CLK0
DDRB_CLK1
DDRB_CLK1#
E16
A17
Y11
W11
8
DDRA_CLK0
MA_CLK_H1
MB_CLK_H1
DDRB_CLK0
9
MB_DATA59
MA_DATA59
DDRA_CLK0#
DDRB_CLK0#
F16
A18
A
E14
AB14
8
DDRA_CLK0#
DDRB_CLK0#
9
MA_CLK_L1
MB_CLK_L1
MB_DATA60
MA_DATA60
Y16
AF18
A
F14
AA14
8
DDRA_CLK1
MA_CLK_H2
MB_CLK_H2
DDRB_CLK1
9
MB_DATA61
MA_DATA61
DDRA_CLK1#
AA16
AF17
A
F11
AB12
8
DDRA_CLK1#
DDRB_CLK1#
9
MA_CLK_L2
MB_CLK_L2
MB_DATA62
MA_DATA62
P19
R26
AD11
AA12
MA_CLK_H3
MB_CLK_H3
MB_DATA63
MA_DATA63
P20
R25
9
DDRB_SDM[7..0]
DDRA_SDM[7..0]
8
MA_CLK_L3
MB_CLK_L3
3
DDRB_SDM0
DDRA_SDM0
3
A12
E12
8
DDRA_SMA[15..0]
DDRB_SMA[15..0]
9
MB_DM0
MA_DM0
DDRA_SMA0
DDRB_SMA0
DDRB_SDM1
DDRA_SDM1
N21
P24
B16
C15
MA_ADD0
MB_ADD0
MB_DM1
MA_DM1
DDRA_SMA1
DDRB_SMA1
DDRB_SDM2
DDRA_SDM2
M20
N24
A22
E19
MA_ADD1
MB_ADD1
MB_DM2
MA_DM2
DDRA_SMA2
DDRA_SMA3
DDRB_SMA2
DDRB_SMA4
DDRB_SDM3
DDRA_SDM3
N22
P26
E25
F24
MA_ADD2
MB_ADD2
MB_DM3
MA_DM3
M19
N23
DDRB_SMA3
DDRB_SMA5
DDRB_SDM4
A
B26
AC24
DDRA_SDM4
MA_ADD3
MB_ADD3
MB_DM4
MA_DM4
DDRA_SMA4
DDRB_SDM5
DDRA_SDM5
M22
N26
A
E22
Y19
MA_ADD4
MB_ADD4
MB_DM5
MA_DM5
DDRA_SMA5
L20
L23
DDRB_SDM6
A
C16
AB16
DDRA_SDM6
MA_ADD5
MB_ADD5
MB_DM6
MA_DM6
DDRA_SMA6
DDRB_SMA6
DDRB_SDM7
DDRA_SDM7
M24
N25
AD12
Y13
MA_ADD6
MB_ADD6
MB_DM7
MA_DM7
DDRA_SMA7
L21
L24
DDRB_SMA7
MA_ADD7
MB_ADD7
DDRA_SMA8
DDRB_SMA8
DDRB_SDQS0
DDRB_SDQS0#
DDRA_SDQS0
DDRA_SDQS0#
L19
M26
C12
G13
MA_ADD8
MB_ADD8
9
DDRB_SDQS0
MB_DQS_H0
MA_DQS_H0
DDRA_SDQS0
8
DDRA_SMA9
DDRB_SMA9
K22
K26
B12
H13
9
DDRB_SDQS0#
DDRA_SDQS0#
8
MA_ADD9
MB_ADD9
MB_DQS_L0
MA_DQS_L0
DDRA_SMA10
DDRB_SMA10
DDRB_SDQS1
DDRB_SDQS1#
DDRA_SDQS1
DDRA_SDQS1#
R21
T26
D16
G16
MA_ADD10
MB_ADD10
9
DDRB_SDQS1
MB_DQS_H1
MA_DQS_H1
DDRA_SDQS1
8
DDRA_SMA11
DDRB_SMA11
L22
L26
C16
G15
9
DDRB_SDQS1#
DDRA_SDQS1#
8
MA_ADD11
MB_ADD11
MB_DQS_L1
MA_DQS_L1
DDRA_SMA12
DDRA_SMA14
DDRB_SMA12
DDRB_SDQS2
DDRB_SDQS2#
DDRA_SDQS2
DDRA_SDQS2#
K20
L25
A24
C22
MA_ADD12
MB_ADD12
9
DDRB_SDQS2
MB_DQS_H2
MA_DQS_H2
DDRA_SDQS2
8
DDRA_SMA13
DDRB_SMA13
V24
W24
A23
C21
9
DDRB_SDQS2#
DDRA_SDQS2#
8
MA_ADD13
MB_ADD13
MB_DQS_L2
MA_DQS_L2
DDRB_SMA14
DDRB_SDQS3
DDRB_SDQS3#
DDRA_SDQS3
DDRA_SDQS3#
K24
J23
F26
G22
MA_ADD14
MB_ADD14
9
DDRB_SDQS3
MB_DQS_H3
MA_DQS_H3
DDRA_SDQS3
8
DDRA_SMA15
DDRB_SMA15
K19
J24
E26
G21
MA_ADD15
MB_ADD15
9
DDRB_SDQS3#
MB_DQS_L3
MA_DQS_L3
DDRA_SDQS3#
8
DDRB_SDQS4
DDRB_SDQS4#
DDRA_SDQS4
DDRA_SDQS4#
DDRA_SDQS5
DDRA_SDQS5#
DDRA_SDQS6
DDRA_SDQS6#
DDRA_SDQS7#
A
C25
AD23
9
DDRB_SDQS4
MB_DQS_H4
MA_DQS_H4
DDRA_SDQS4
8
DDRA_SBS0#
DDRB_SBS0#
DDRB_SBS1#
DDRB_SBS2#
R20
R24
A
C26
AC23
8
DDRA_SBS0#
MA_BANK0
MB_BANK0
DDRB_SBS0#
9
9
DDRB_SDQS4#
MB_DQS_L4
MA_DQS_L4
DDRA_SDQS4#
8
DDRA_SBS1#
R23
U26
DDRB_SDQS5
DDRB_SDQS5#
A
F21
AB19
8
DDRA_SBS1#
MA_BANK1
MB_BANK1
DDRB_SBS1#
9
9
DDRB_SDQS5
MB_DQS_H5
MA_DQS_H5
DDRA_SDQS5
8
DDRA_SBS2#
J21
J26
A
F22
AB20
8
DDRA_SBS2#
MA_BANK2
MB_BANK2
DDRB_SBS2#
9
9
DDRB_SDQS5#
MB_DQS_L5
MA_DQS_L5
DDRA_SDQS5#
8
DDRB_SDQS6
DDRB_SDQS6#
A
E16
Y15
9
DDRB_SDQS6
DDRA_SDQS6
8
MB_DQS_H6
MA_DQS_H6
DDRA_SRAS#
DDRB_SRAS#
DDRB_SCAS#
DDRB_SWE#
R19
U25
A
D16
W15
8
DDRA_SRAS#
MA_RAS_L
MB_RAS_L
DDRB_SRAS#
9
9
DDRB_SDQS6#
MB_DQS_L6
MA_DQS_L6
DDRA_SDQS6#
8
DDRA_SCAS#
DDRB_SDQS7
DDRB_SDQS7#
DDRA_SDQS7
T22
U24
A
F12
W12
8
DDRA_SCAS#
DDRB_SCAS#
9
9
DDRB_SDQS7
DDRA_SDQS7
8
MA_CAS_L
MB_CAS_L
MB_DQS_H7
MA_DQS_H7
DDRA_SWE#
T24
U23
AE12
W13
8
DDRA_SWE#
MA_WE_L
MB_WE_L
DDRB_SWE#
9
9
DDRB_SDQS7#
MB_DQS_L7
MA_DQS_L7
DDRA_SDQS7#
8
6090022100G_B
conn@
6090022100G_B
conn@
6090022100G_B
conn@
6090022100G_B
conn@
4
4
Compal Electronics, Inc.
Compal Electronics, Inc.
Compal Electronics, Inc.
Security Classification
Security Classification
Security Classification
Compal Secret Data
Compal Secret Data
Compal Secret Data
2008/10/06
2008/10/06
2008/10/06
2009/10/06
2009/10/06
2009/10/06
Title
Title
Title
Issued Date
Issued Date
Issued Date
Deciphered Date
Deciphered Date
Deciphered Date
AMD CPU S1G3 DDRII I/F
AMD CPU S1G3 DDRII I/F
AMD CPU S1G3 DDRII I/F
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Size
Size
Size
Document Number
Document Number
Document Number
Rev
Rev
Rev
NBLG0 LA-5521P
NBLG0 LA-5521P
NBLG0 LA-5521P
Custom
Custom
Custom
0.1
0.1
0.1
Date:
Date:
Date:
Thursday, June 04, 2009
Thursday, June 04, 2009
Thursday, June 04, 2009
Sheet
Sheet
Sheet
5
5
5
of
of
of
58
58
58
A
B
C
D
E
Plik z chomika:
daro_tt
Inne pliki z tego folderu:
Acer Aspire 4535_Compal_LA-4921P_KBLG0_NBLG0_Rev1.0.pdf
(13932 KB)
05_Schematic_Diagram (1).pdf
(2473 KB)
20050617181943203_7_Schematic_Diagrams.PDF
(20545 KB)
05_Schematic_Diagram.pdf
(26969 KB)
5_Schemetic_Diagram (1).pdf
(34094 KB)
Inne foldery tego chomika:
Acer
acer (lev3)
Asus
Compaq (lev3)
Compaq-HP
Zgłoś jeśli
naruszono regulamin