# # $Id: 64doc,v 1.8 1994/06/03 19:50:04 jopi Exp $ # # This file is part of Commodore 64 emulator # and Program Development System. # # See README for copyright notice # # This file contains documentation for 6502/6510/8500/8502 instruction set. # # # Written by # John West (john@ucc.gu.uwa.edu.au) # Marko Mäkelä (msmakela@cc.hut.fi) # # # $Log: 64doc,v $ # Revision 1.8 1994/06/03 19:50:04 jopi # Patchlevel 2 # # Revision 1.7 1994/04/15 13:07:04 jopi # 65xx Register descriptions added # # Revision 1.6 1994/02/18 16:09:36 jopi # # Revision 1.5 1994/01/26 16:08:37 jopi # X64 version 0.2 PL 1 # # Revision 1.4 1993/11/10 01:55:34 jopi # # Revision 1.3 93/06/21 13:37:18 jopi # X64 version 0.2 PL 0 # # Revision 1.2 93/06/21 13:07:15 jopi # *** empty log message *** # # Note: To extract the uuencoded ML programs in this article most easily you may use e.g. "uud" by Edwin Kremer <edwin@zlotty>, which extracts them all at once. Documentation for the NMOS 65xx/85xx Instruction Set 6510 Instructions by Addressing Modes 6502 Registers 6510/8502 Undocumented Commands Register selection for load and store Decimal mode in NMOS 6500 series 6510 features Different CPU types 6510 Instruction Timing How Real Programmers Acknowledge Interrupts Memory Management Autostart Code Notes References 6510 Instructions by Addressing Modes off- ++++++++++ Positive ++++++++++ ---------- Negative ---------- set 00 20 40 60 80 a0 c0 e0 mode +00 BRK JSR RTI RTS NOP* LDY CPY CPX Impl/immed +01 ORA AND EOR ADC STA LDA CMP SBC (indir,x) +02 t t t t NOP*t LDX NOP*t NOP*t ? /immed +03 SLO* RLA* SRE* RRA* SAX* LAX* DCP* ISB* (indir,x) +04 NOP* BIT NOP* NOP* STY LDY CPY CPX Zeropage +05 ORA AND EOR ADC STA LDA CMP SBC Zeropage +06 ASL ROL LSR ROR STX LDX DEC INC Zeropage +07 SLO* RLA* SRE* RRA* SAX* LAX* DCP* ISB* Zeropage +08 PHP PLP PHA PLA DEY TAY INY INX Implied +09 ORA AND EOR ADC NOP* LDA CMP SBC Immediate +0a ASL ROL LSR ROR TXA TAX DEX NOP Accu/impl +0b ANC** ANC** ASR** ARR** ANE** LXA** SBX** SBC* Immediate +0c NOP* BIT JMP JMP () STY LDY CPY CPX Absolute +0d ORA AND EOR ADC STA LDA CMP SBC Absolute +0e ASL ROL LSR ROR STX LDX DEC INC Absolute +0f SLO* RLA* SRE* RRA* SAX* LAX* DCP* ISB* Absolute +10 BPL BMI BVC BVS BCC BCS BNE BEQ Relative +11 ORA AND EOR ADC STA LDA CMP SBC (indir),y +12 t t t t t t t t ? +13 SLO* RLA* SRE* RRA* SHA** LAX* DCP* ISB* (indir),y +14 NOP* NOP* NOP* NOP* STY LDY NOP* NOP* Zeropage,x +15 ORA AND EOR ADC STA LDA CMP SBC Zeropage,x +16 ASL ROL LSR ROR STX y) LDX y) DEC INC Zeropage,x +17 SLO* RLA* SRE* RRA* SAX* y) LAX* y) DCP* ISB* Zeropage,x +18 CLC SEC CLI SEI TYA CLV CLD SED Implied +19 ORA AND EOR ADC STA LDA CMP SBC Absolute,y +1a NOP* NOP* NOP* NOP* TXS TSX NOP* NOP* Implied +1b SLO* RLA* SRE* RRA* SHS** LAS** DCP* ISB* Absolute,y +1c NOP* NOP* NOP* NOP* SHY** LDY NOP* NOP* Absolute,x +1d ORA AND EOR ADC STA LDA CMP SBC Absolute,x +1e ASL ROL LSR ROR SHX**y) LDX y) DEC INC Absolute,x +1f SLO* RLA* SRE* RRA* SHA**y) LAX* y) DCP* ISB* Absolute,x ROR intruction is available on MC650x microprocessors after June, 1976. Legend: t Jams the machine *t Jams very rarely * Undocumented command ** Unusual operation y) indexed using Y instead of X () indirect instead of absolute Note that the NOP instructions do have other addressing modes than the implied addressing. The NOP instruction is just like any other load instruction, except it does not store the result anywhere nor affects the flags. 6502 Registers The NMOS 65xx processors are not ruined with too many registers. In addition to that, the registers are mostly 8-bit. Here is a brief description of each register: PC Program Counter This register points the address from which the next instruction byte (opcode or parameter) will be fetched. Unlike other registers, this one is 16 bits in length. The low and high 8-bit halves of the register are called PCL and PCH, respectively. The Program Counter may be read by pushing its value on the stack. This can be done either by jumping to a subroutine or by causing an interrupt. S Stack pointer The NMOS 65xx processors have 256 bytes of stack memory, ranging from $0100 to $01FF. The S register is a 8-bit offset to the stack page. In other words, whenever anything is being pushed on the stack, it will be stored to the address $0100+S. The Stack pointer can be read and written by transfering its value to or from the index register X (see below) with the TSX and TXS instructions. P Processor status This 8-bit register stores the state of the processor. The bits in this register are called flags. Most of the flags have something to do with arithmetic operations. The P register can be read by pushing it on the stack (with PHP or by causing an interrupt). If you only need to read one flag, you can use the branch instructions. Setting the flags is possible by pulling the P register from stack or by using the flag set or clear instructions. Following is a list of the flags, starting from the 8th bit of the P register (bit 7, value $80): N Negative flag This flag will be set after any arithmetic operations (when any of the registers A, X or Y is being loaded with a value). Generally, the N flag will be copied from the topmost bit of the register being loaded. Note that TXS (Transfer X to S) is not an arithmetic operation. Also note that the BIT instruction affects the Negative flag just like arithmetic operations. Finally, the Negative flag behaves differently in Decimal operations (see description below). V oVerflow flag Like the Negative flag, this flag is intended to be used with 8-bit signed integer numbers. The flag will be affected by addition and subtraction, the instructions PLP, CLV and BIT, and the hardware signal -SO. Note that there is no SEV instruction, even though the MOS engineers loved to use East European abbreviations, like DDR (Deutsche Demokratische Republik vs. Data Direction Register). (The Russian abbreviation for their former trade association COMECON is SEV.) The -SO (Set Overflow) signal is available on some processors, at least the 6502, to set the V flag. This enables response to an I/O activity in equal or less than three clock cycles when using a BVC instruction branching to itself ($50 $FE). The CLV instruction clears the V flag, and the PLP and BIT instructions copy the flag value from the bit 6 of the topmost stack entry or from memory. After a binary addition or subtraction, the V flag will be set on a sign overflow, cleared otherwise. What is a sign overflow? For instance, if you are trying to add 123 and 45 together, the result (168) does not fit in a 8-bit signed integer (upper limit 127 and lower limit -128). Similarly, adding -123 to -45 causes the overflow, just like subtracting -45 from 123 or 123 from -45 would do. Like the N flag, the V flag will not be set as expected in the Decimal mode. Later in this document is a precise operation description. A common misbelief is that the V flag could only be set by arithmetic operations, not cleared. 1 unused flag To the current knowledge, this flag is always 1. B Break flag This flag is used to distinguish software (BRK) interrupts from hardware interrupts (IRQ or NMI). The ...
Amiga7878