*===============================================================================* WD65C816 Opcode Reference Transcribed by Charles T. Turley 11/23/98 *===============================================================================* Cycle Time Adjustments 16A: Add 1 if using 16-bit memory and accumulator 16B: Add 2 if using 16-bit memory and accumulator B: Add 1 if conditional branch is taken C: Add 1 if index crosses bank boundary D: Add 1 if status register's Decimal bit is set I: Add 1 if using 16-bit index registers M: Add 7 for each byte copied N: Add 1 if in native mode P: Add 1 if branch crosses page boundary in emulation mode Z: Add 1 if DP is not on a page boundary Instruction Hex Cycle Time Status Reg. Notes *===============================================================================* ADC #imm 69 2 [16A,D] nv----zc Add memory to A with carry. ADC abs 6D 4 [16A,D] ADC longabs 6F 5 [16A,D] ADC dp 65 3 [16A,Z,D] ADC (dp) 72 5 [16A,Z,D] ADC [dp] 67 6 [16A,Z,D] ADC abs,X 7D 4 [16A,C,D] ADC abslong,X 7F 5 [16A,D] ADC abs,Y 79 4 [16A,C,D] ADC dp,X 75 4 [16A,Z,D] ADC (dp,X) 61 6 [16A,Z,D] ADC (dp),Y 71 5 [16A,Z,C,D] ADC [dp],Y 77 6 [16A,Z,D] ADC ofs,S 63 4 [16A,D] ADC (ofs,S),Y 73 7 [16A,D] *-------------------------------------------------------------------------------* AND #imm 29 2 [16A] n-----z- And A with memory. AND abs 2D 4 [16A] AND abslong 2F 5 [16A] AND dp 25 3 [16A,Z] AND (dp) 32 5 [16A,Z] AND [dp] 27 6 [16A,Z] AND abs,X 3D 4 [16A,C] AND abslong,X 3F 5 [16A] AND abs,Y 39 4 [16A,C] AND dp,X 35 4 [16A,Z] AND (dp,X) 21 6 [16A,Z] AND (dp),Y 31 5 [16A,Z,C] AND [dp],Y 37 6 [16A,Z] AND ofs,S 23 4 [16A] AND (ofs,S),Y 33 7 [16A] *-------------------------------------------------------------------------------* ASL 0A 2 n-----zc Shift left memory or A. ASL abs 0E 6 [16B] ASL dp 06 5 [16B,Z] ASL abs,X 1E 7 [16B] ASL dp,X 16 6 [16B,Z] *-------------------------------------------------------------------------------* BCC relbyte 90 2 [B,P] -------- Branch if carry clear. BCS relbyte B0 2 [B,P] -------- Branch if carry set. BEQ relbyte F0 2 [B,P] -------- Branch if equal (z=0). *-------------------------------------------------------------------------------* BIT #imm 89 2 [16A] ------z- Test memory with bits from A. BIT abs 2C 4 [16A] nv----z- BIT dp 24 3 [16A,Z] BIT abs,X 3C 4 [16A,C] BIT dp,X 34 4 [16A,Z] *-------------------------------------------------------------------------------* BMI relbyte 30 2 [B,P] -------- Branch if minus (n=1). BNE relbyte D0 2 [B,P] -------- Branch if not equal. BPL relbyte 10 2 [B,P] -------- Branch if positive. BRA relbyte 80 2 [P] -------- Branch always. *-------------------------------------------------------------------------------* BRK byte 00 7 [N] ----01-- Software break BRK 00 ---101-- (sets b in emulation mode). *-------------------------------------------------------------------------------* BRL relword 82 4 -------- Branch always long. BVC relbyte 50 2 [B,P] -------- Branch if overflow clear. BVS relbyte 70 2 [B,P] -------- Branch if overflow set. *-------------------------------------------------------------------------------* CLC 18 2 -------0 Clear carry bit. CLD D8 2 ----0--- Clear decimal bit. CLI 58 2 -----0-- Clear interrupt disable bit. CLV B8 2 -0------ Clear overflow bit. *-------------------------------------------------------------------------------* CMP #imm C9 2 [16A] n-----zc Compare A with memory. CMP abs CD 4 [16A] CMP abslong CF 5 [16A] CMP dp C5 3 [16A,Z] CMP (dp) D2 5 [16A,Z] CMP [dp] C7 6 [16A,Z] CMP abs,X DD 4 [16A,C] CMP abslong,X DF 5 [16A] CMP abs,Y D9 4 [16A,C] CMP dp,X D5 4 [16A,Z] CMP (dp,X) C1 6 [16A,Z] CMP (dp),Y D1 5 [16A,Z,C] CMP [dp],Y D7 6 [16A,Z] CMP ofs,S C3 4 [16A] CMP (ofs,S),Y D3 7 [16A] *-------------------------------------------------------------------------------* COP byte 02 7 [N] ----01-- Coprocessor enable. *-------------------------------------------------------------------------------* CPX #imm E0 2 [I] n-----zc Compare X with memory. CPX abs EC 4 [I] CPX dp E4 3 [I,Z] *-------------------------------------------------------------------------------* CPY #imm C0 2 [I] n-----zc Compare Y with memory. CPY abs CC 4 [I] CPY dp C4 3 [I,Z] *-------------------------------------------------------------------------------* DEC 3A 2 n------c Decrement A or memory. DEC abs CE 6 [16B] DEC dp C6 5 [16B,Z] DEC abs,X DE 7 [16B] DEC dp,X D6 6 [16B,Z] *-------------------------------------------------------------------------------* DEX CA 2 n------c Decrement X register. DEY 88 2 n------c Decrement Y register. *-------------------------------------------------------------------------------* EOR #imm 49 2 [16A] n------c Exclusive-OR A with memory. EOR abs 4D 4 [16A] EOR abslong 4F 5 [16A] EOR dp 45 3 [16A,Z] EOR (dp) 52 6 [16A,Z] EOR [dp] 47 6 [16A,Z] EOR abs,X 5D 4 [16A,C] EOR abslong,X 5F 5 [16A] EOR abs,Y 59 4 [16A,C] EOR dp,X 55 4 [16A,Z] EOR (dp,X) 41 5 [16A,Z] EOR (dp),Y 51 6 [16A,Z,C] EOR [dp],Y 57 4 [16A,Z] EOR ofs,S 43 4 [16A] EOR (ofs,S),Y 53 7 [16A] *-------------------------------------------------------------------------------* INC 1A 2 n------c Increment A or memory. INC abs EE 6 [16B] INC dp E6 5 [16B,Z] INC abs,X FE 7 [16B] INC dp,X F6 6 [16B,Z] *-------------------------------------------------------------------------------* INX E8 2 n------c Increment X register. INY C8 2 n------c Increment Y register. *-------------------------------------------------------------------------------* JMP abs 4C 3 -------- Jump. JMP (abs) 6C 5 JMP (abs,X) 7C 6 *-------------------------------------------------------------------------------* JML abslong 5C 4 -------- Jump long. JML [dp] DC 6 *-------------------------------------------------------------------------------* JSL abslong 22 8 -------- Jump to subroutine long. *-------------------------------------------------------------------------------* JSR abs 20 6 -------- Jump to subroutine. JSR (addr,X) FC 8 *-------------------------------------------------------------------------------* LDA #imm A9 2 [16A] n-----z- Load accumulator with memory. LDA abs AD 4 [16A] LDA abslong AF 5 [16A] LDA dp A5 3 [16A,Z] LDA (dp) B2 5 [16A,Z] LDA [dp] A7 6 [16A,Z] LDA abs,X BD 4 [16A,C] LDA abslong,X BF 5 [16A] LDA abs,Y B9 4 [16A,C] LDA dp,X B5 4 [16A,Z] LDA (dp,X) A1 6 [16A,Z] LDA (dp),Y B1 5 [16A,Z,C] LDA [dp],Y B7 6 [16A,Z] LDA ofs,S A3 4 [16A] LDA (ofs,S),Y B3 7 [16A] *-------------------------------------------------------------------------------* LDX #imm A2 2 [I] n-----z- Load X register with memory. LDX abs AE 4 [I] LDX dp A6 3 [I,Z] LDX abs,Y ...
Amiga7878